/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#ifndef __DRIVERS_PINCTRL_ROCKCHIP_H
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#define __DRIVERS_PINCTRL_ROCKCHIP_H
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <linux/types.h>
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#define RK_GPIO0_A0 0
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#define RK_GPIO0_A1 1
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#define RK_GPIO0_A2 2
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#define RK_GPIO0_A3 3
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#define RK_GPIO0_A4 4
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#define RK_GPIO0_A5 5
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#define RK_GPIO0_A6 6
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#define RK_GPIO0_A7 7
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#define RK_GPIO0_B0 8
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#define RK_GPIO0_B1 9
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#define RK_GPIO0_B2 10
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#define RK_GPIO0_B3 11
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#define RK_GPIO0_B4 12
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#define RK_GPIO0_B5 13
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#define RK_GPIO0_B6 14
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#define RK_GPIO0_B7 15
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#define RK_GPIO0_C0 16
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#define RK_GPIO0_C1 17
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#define RK_GPIO0_C2 18
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#define RK_GPIO0_C3 19
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#define RK_GPIO0_C4 20
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#define RK_GPIO0_C5 21
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#define RK_GPIO0_C6 22
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#define RK_GPIO0_C7 23
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#define RK_GPIO0_D0 24
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#define RK_GPIO0_D1 25
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#define RK_GPIO0_D2 26
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#define RK_GPIO0_D3 27
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#define RK_GPIO0_D4 28
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#define RK_GPIO0_D5 29
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#define RK_GPIO0_D6 30
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#define RK_GPIO0_D7 31
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#define RK_GPIO1_A0 32
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#define RK_GPIO1_A1 33
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#define RK_GPIO1_A2 34
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#define RK_GPIO1_A3 35
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#define RK_GPIO1_A4 36
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#define RK_GPIO1_A5 37
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#define RK_GPIO1_A6 38
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#define RK_GPIO1_A7 39
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#define RK_GPIO1_B0 40
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#define RK_GPIO1_B1 41
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#define RK_GPIO1_B2 42
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#define RK_GPIO1_B3 43
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#define RK_GPIO1_B4 44
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#define RK_GPIO1_B5 45
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#define RK_GPIO1_B6 46
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#define RK_GPIO1_B7 47
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#define RK_GPIO1_C0 48
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#define RK_GPIO1_C1 49
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#define RK_GPIO1_C2 50
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#define RK_GPIO1_C3 51
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#define RK_GPIO1_C4 52
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#define RK_GPIO1_C5 53
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#define RK_GPIO1_C6 54
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#define RK_GPIO1_C7 55
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#define RK_GPIO1_D0 56
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#define RK_GPIO1_D1 57
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#define RK_GPIO1_D2 58
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#define RK_GPIO1_D3 59
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#define RK_GPIO1_D4 60
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#define RK_GPIO1_D5 61
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#define RK_GPIO1_D6 62
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#define RK_GPIO1_D7 63
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#define RK_GPIO2_A0 64
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#define RK_GPIO2_A1 65
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#define RK_GPIO2_A2 66
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#define RK_GPIO2_A3 67
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#define RK_GPIO2_A4 68
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#define RK_GPIO2_A5 69
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#define RK_GPIO2_A6 70
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#define RK_GPIO2_A7 71
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#define RK_GPIO2_B0 72
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#define RK_GPIO2_B1 73
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#define RK_GPIO2_B2 74
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#define RK_GPIO2_B3 75
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#define RK_GPIO2_B4 76
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#define RK_GPIO2_B5 77
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#define RK_GPIO2_B6 78
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#define RK_GPIO2_B7 79
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#define RK_GPIO2_C0 80
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#define RK_GPIO2_C1 81
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#define RK_GPIO2_C2 82
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#define RK_GPIO2_C3 83
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#define RK_GPIO2_C4 84
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#define RK_GPIO2_C5 85
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#define RK_GPIO2_C6 86
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#define RK_GPIO2_C7 87
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#define RK_GPIO2_D0 88
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#define RK_GPIO2_D1 89
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#define RK_GPIO2_D2 90
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#define RK_GPIO2_D3 91
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#define RK_GPIO2_D4 92
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#define RK_GPIO2_D5 93
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#define RK_GPIO2_D6 94
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#define RK_GPIO2_D7 95
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#define RK_GPIO3_A0 96
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#define RK_GPIO3_A1 97
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#define RK_GPIO3_A2 98
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#define RK_GPIO3_A3 99
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#define RK_GPIO3_A4 100
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#define RK_GPIO3_A5 101
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#define RK_GPIO3_A6 102
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#define RK_GPIO3_A7 103
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#define RK_GPIO3_B0 104
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#define RK_GPIO3_B1 105
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#define RK_GPIO3_B2 106
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#define RK_GPIO3_B3 107
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#define RK_GPIO3_B4 108
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#define RK_GPIO3_B5 109
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#define RK_GPIO3_B6 110
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#define RK_GPIO3_B7 111
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#define RK_GPIO3_C0 112
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#define RK_GPIO3_C1 113
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#define RK_GPIO3_C2 114
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#define RK_GPIO3_C3 115
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#define RK_GPIO3_C4 116
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#define RK_GPIO3_C5 117
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#define RK_GPIO3_C6 118
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#define RK_GPIO3_C7 119
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#define RK_GPIO3_D0 120
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#define RK_GPIO3_D1 121
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#define RK_GPIO3_D2 122
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#define RK_GPIO3_D3 123
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#define RK_GPIO3_D4 124
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#define RK_GPIO3_D5 125
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#define RK_GPIO3_D6 126
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#define RK_GPIO3_D7 127
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#define RK_GPIO4_A0 128
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#define RK_GPIO4_A1 129
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#define RK_GPIO4_A2 130
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#define RK_GPIO4_A3 131
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#define RK_GPIO4_A4 132
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#define RK_GPIO4_A5 133
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#define RK_GPIO4_A6 134
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#define RK_GPIO4_A7 135
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#define RK_GPIO4_B0 136
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#define RK_GPIO4_B1 137
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#define RK_GPIO4_B2 138
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#define RK_GPIO4_B3 139
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#define RK_GPIO4_B4 140
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#define RK_GPIO4_B5 141
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#define RK_GPIO4_B6 142
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#define RK_GPIO4_B7 143
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#define RK_GPIO4_C0 144
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#define RK_GPIO4_C1 145
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#define RK_GPIO4_C2 146
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#define RK_GPIO4_C3 147
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#define RK_GPIO4_C4 148
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#define RK_GPIO4_C5 149
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#define RK_GPIO4_C6 150
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#define RK_GPIO4_C7 151
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#define RK_GPIO4_D0 152
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#define RK_GPIO4_D1 153
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#define RK_GPIO4_D2 154
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#define RK_GPIO4_D3 155
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#define RK_GPIO4_D4 156
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#define RK_GPIO4_D5 157
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#define RK_GPIO4_D6 158
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#define RK_GPIO4_D7 159
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#define RK_GENMASK_VAL(h, l, v) \
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(GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
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/**
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* Encode variants of iomux registers into a type variable
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*/
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#define IOMUX_GPIO_ONLY BIT(0)
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#define IOMUX_WIDTH_4BIT BIT(1)
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#define IOMUX_SOURCE_PMU BIT(2)
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#define IOMUX_UNROUTED BIT(3)
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#define IOMUX_WIDTH_3BIT BIT(4)
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#define IOMUX_8WIDTH_2BIT BIT(5)
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#define IOMUX_WRITABLE_32BIT BIT(6)
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#define IOMUX_L_SOURCE_PMU BIT(7)
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/**
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* Defined some common pins constants
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*/
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#define ROCKCHIP_PULL_BITS_PER_PIN 2
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#define ROCKCHIP_PULL_PINS_PER_REG 8
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#define ROCKCHIP_PULL_BANK_STRIDE 16
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#define ROCKCHIP_DRV_BITS_PER_PIN 2
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#define ROCKCHIP_DRV_PINS_PER_REG 8
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#define ROCKCHIP_DRV_BANK_STRIDE 16
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#define ROCKCHIP_DRV_3BITS_PER_PIN 3
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/**
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* @type: iomux variant using IOMUX_* constants
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* @offset: if initialized to -1 it will be autocalculated, by specifying
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* an initial offset value the relevant source offset can be reset
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* to a new value for autocalculating the following iomux registers.
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*/
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struct rockchip_iomux {
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int type;
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int offset;
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};
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#define DRV_TYPE_IO_MASK GENMASK(31, 16)
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#define DRV_TYPE_WRITABLE_32BIT BIT(31)
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/**
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* enum type index corresponding to rockchip_perpin_drv_list arrays index.
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*/
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enum rockchip_pin_drv_type {
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DRV_TYPE_IO_DEFAULT = 0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_3V0_AUTO,
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DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_MAX
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};
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#define PULL_TYPE_IO_MASK GENMASK(31, 16)
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#define PULL_TYPE_WRITABLE_32BIT BIT(31)
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/**
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* enum type index corresponding to rockchip_pull_list arrays index.
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*/
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enum rockchip_pin_pull_type {
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PULL_TYPE_IO_DEFAULT = 0,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_MAX
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};
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/**
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* enum mux route register type, should be invalid/default/topgrf/pmugrf.
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* INVALID: means do not need to set mux route
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* DEFAULT: means same regmap as pin iomux
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* TOPGRF: means mux route setting in topgrf
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* PMUGRF: means mux route setting in pmugrf
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*/
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enum rockchip_pin_route_type {
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ROUTE_TYPE_DEFAULT = 0,
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ROUTE_TYPE_TOPGRF = 1,
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ROUTE_TYPE_PMUGRF = 2,
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ROUTE_TYPE_INVALID = -1,
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};
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/**
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* @drv_type: drive strength variant using rockchip_perpin_drv_type
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* @offset: if initialized to -1 it will be autocalculated, by specifying
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* an initial offset value the relevant source offset can be reset
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* to a new value for autocalculating the following drive strength
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* registers. if used chips own cal_drv func instead to calculate
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* registers offset, the variant could be ignored.
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*/
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struct rockchip_drv {
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enum rockchip_pin_drv_type drv_type;
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int offset;
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};
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/**
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* @priv: common pinctrl private basedata
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* @pin_base: first pin number
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* @nr_pins: number of pins in this bank
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* @name: name of the bank
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* @bank_num: number of the bank, to account for holes
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* @iomux: array describing the 4 iomux sources of the bank
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* @drv: array describing the 4 drive strength sources of the bank
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* @pull_type: array describing the 4 pull type sources of the bank
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* @recalced_mask: bits describing the mux recalced pins of per bank
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* @route_mask: bits describing the routing pins of per bank
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*/
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struct rockchip_pin_bank {
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struct rockchip_pinctrl_priv *priv;
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u32 pin_base;
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u8 nr_pins;
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char *name;
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u8 bank_num;
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struct rockchip_iomux iomux[4];
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struct rockchip_drv drv[4];
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enum rockchip_pin_pull_type pull_type[4];
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u32 recalced_mask;
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u32 route_mask;
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};
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#define PIN_BANK(id, pins, label) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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}, \
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}
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#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = -1 }, \
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{ .type = iom1, .offset = -1 }, \
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{ .type = iom2, .offset = -1 }, \
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{ .type = iom3, .offset = -1 }, \
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}, \
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}
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#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
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iom3, offset0, offset1, offset2, \
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offset3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = offset0 }, \
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{ .type = iom1, .offset = offset1 }, \
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{ .type = iom2, .offset = offset2 }, \
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{ .type = iom3, .offset = offset3 }, \
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}, \
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}
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#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = type0, .offset = -1 }, \
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{ .drv_type = type1, .offset = -1 }, \
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{ .drv_type = type2, .offset = -1 }, \
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{ .drv_type = type3, .offset = -1 }, \
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}, \
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}
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#define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
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iom2, iom3, pull0, pull1, \
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pull2, pull3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = -1 }, \
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{ .type = iom1, .offset = -1 }, \
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{ .type = iom2, .offset = -1 }, \
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{ .type = iom3, .offset = -1 }, \
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}, \
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.pull_type[0] = pull0, \
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.pull_type[1] = pull1, \
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.pull_type[2] = pull2, \
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.pull_type[3] = pull3, \
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}
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#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
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drv2, drv3, pull0, pull1, \
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pull2, pull3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = drv0, .offset = -1 }, \
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{ .drv_type = drv1, .offset = -1 }, \
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{ .drv_type = drv2, .offset = -1 }, \
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{ .drv_type = drv3, .offset = -1 }, \
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}, \
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.pull_type[0] = pull0, \
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.pull_type[1] = pull1, \
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.pull_type[2] = pull2, \
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.pull_type[3] = pull3, \
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}
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#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
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iom2, iom3, drv0, drv1, drv2, \
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drv3, offset0, offset1, \
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offset2, offset3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = -1 }, \
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{ .type = iom1, .offset = -1 }, \
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{ .type = iom2, .offset = -1 }, \
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{ .type = iom3, .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = drv0, .offset = offset0 }, \
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{ .drv_type = drv1, .offset = offset1 }, \
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{ .drv_type = drv2, .offset = offset2 }, \
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{ .drv_type = drv3, .offset = offset3 }, \
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}, \
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}
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#define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \
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iom2, iom3, drv0, drv1, drv2, \
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drv3, pull0, pull1, pull2, \
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pull3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = -1 }, \
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{ .type = iom1, .offset = -1 }, \
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{ .type = iom2, .offset = -1 }, \
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{ .type = iom3, .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = drv0, .offset = -1 }, \
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{ .drv_type = drv1, .offset = -1 }, \
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{ .drv_type = drv2, .offset = -1 }, \
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{ .drv_type = drv3, .offset = -1 }, \
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}, \
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.pull_type[0] = pull0, \
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.pull_type[1] = pull1, \
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.pull_type[2] = pull2, \
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.pull_type[3] = pull3, \
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}
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#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
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label, iom0, iom1, iom2, \
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iom3, drv0, drv1, drv2, \
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drv3, offset0, offset1, \
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offset2, offset3, pull0, \
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pull1, pull2, pull3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = -1 }, \
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{ .type = iom1, .offset = -1 }, \
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{ .type = iom2, .offset = -1 }, \
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{ .type = iom3, .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = drv0, .offset = offset0 }, \
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{ .drv_type = drv1, .offset = offset1 }, \
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{ .drv_type = drv2, .offset = offset2 }, \
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{ .drv_type = drv3, .offset = offset3 }, \
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}, \
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.pull_type[0] = pull0, \
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.pull_type[1] = pull1, \
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.pull_type[2] = pull2, \
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.pull_type[3] = pull3, \
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}
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#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
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{ \
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.bank_num = ID, \
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.pin = PIN, \
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.func = FUNC, \
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.route_offset = REG, \
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.route_val = VAL, \
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.route_type = FLAG, \
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}
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#define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \
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PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT)
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#define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \
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PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF)
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#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \
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PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
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#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
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PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
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/**
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* struct rockchip_mux_recalced_data: recalculate a pin iomux data.
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* @num: bank number.
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* @pin: pin number.
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* @reg: register offset.
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* @bit: index at register.
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* @mask: mask bit
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*/
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struct rockchip_mux_recalced_data {
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u8 num;
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u8 pin;
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u32 reg;
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u8 bit;
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u8 mask;
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};
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/**
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* struct rockchip_mux_route_data: route a pin iomux data.
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* @bank_num: bank number.
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* @pin: index at register or used to calc index.
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* @func: the min pin.
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* @route_type: the register type.
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* @route_offset: the max pin.
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* @route_val: the register offset.
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*/
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struct rockchip_mux_route_data {
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u8 bank_num;
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u8 pin;
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u8 func;
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enum rockchip_pin_route_type route_type : 8;
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u32 route_offset;
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u32 route_val;
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};
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/**
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*/
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struct rockchip_pin_ctrl {
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struct rockchip_pin_bank *pin_banks;
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u32 nr_banks;
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u32 nr_pins;
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int grf_mux_offset;
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int pmu_mux_offset;
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int grf_drv_offset;
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int pmu_drv_offset;
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struct rockchip_mux_recalced_data *iomux_recalced;
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u32 niomux_recalced;
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struct rockchip_mux_route_data *iomux_routes;
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u32 niomux_routes;
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int (*set_mux)(struct rockchip_pin_bank *bank,
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int pin, int mux);
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int (*set_pull)(struct rockchip_pin_bank *bank,
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int pin_num, int pull);
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int (*set_drive)(struct rockchip_pin_bank *bank,
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int pin_num, int strength);
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int (*set_schmitt)(struct rockchip_pin_bank *bank,
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int pin_num, int enable);
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};
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/**
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*/
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struct rockchip_pinctrl_priv {
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struct rockchip_pin_ctrl *ctrl;
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struct regmap *regmap_base;
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struct regmap *regmap_pmu;
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};
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extern const struct pinctrl_ops rockchip_pinctrl_ops;
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int rockchip_pinctrl_probe(struct udevice *dev);
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void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
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int *reg, u8 *bit, int *mask);
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int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask);
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int rockchip_translate_drive_value(int type, int strength);
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int rockchip_translate_pull_value(int type, int pull);
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#endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */
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