// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2022 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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static int rk3562_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask;
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u8 bit;
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u32 data;
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debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
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regmap = priv->regmap_base;
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reg = bank->iomux[iomux_num].offset;
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if ((pin % 8) >= 4)
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reg += 0x4;
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bit = (pin % 4) * 4;
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mask = 0xf;
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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/* force jtag m1 */
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if (bank->bank_num == 1) {
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if ((pin == 13) || (pin == 14)) {
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if (mux == 1) {
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regmap_write(regmap, 0x504, 0x10001);
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} else {
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regmap_write(regmap, 0x504, 0x10000);
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}
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}
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}
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debug("iomux write reg = %x data = %x\n", reg, data);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3562_DRV_BITS_PER_PIN 8
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#define RK3562_DRV_PINS_PER_REG 2
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#define RK3562_DRV_GPIO0_OFFSET 0x20070
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#define RK3562_DRV_GPIO1_OFFSET 0x200
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#define RK3562_DRV_GPIO2_OFFSET 0x240
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#define RK3562_DRV_GPIO3_OFFSET 0x10280
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#define RK3562_DRV_GPIO4_OFFSET 0x102C0
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static void rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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switch (bank->bank_num) {
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case 0:
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*reg = RK3562_DRV_GPIO0_OFFSET;
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break;
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case 1:
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*reg = RK3562_DRV_GPIO1_OFFSET;
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break;
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case 2:
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*reg = RK3562_DRV_GPIO2_OFFSET;
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break;
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case 3:
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*reg = RK3562_DRV_GPIO3_OFFSET;
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break;
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case 4:
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*reg = RK3562_DRV_GPIO4_OFFSET;
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break;
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default:
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*reg = 0;
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dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
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break;
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}
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*reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RK3562_DRV_PINS_PER_REG;
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*bit *= RK3562_DRV_BITS_PER_PIN;
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}
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static int rk3562_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data;
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u8 bit;
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int drv = (1 << (strength + 1)) - 1;
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rk3562_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3562_DRV_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (drv << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3562_PULL_BITS_PER_PIN 2
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#define RK3562_PULL_PINS_PER_REG 8
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#define RK3562_PULL_GPIO0_OFFSET 0x20020
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#define RK3562_PULL_GPIO1_OFFSET 0x80
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#define RK3562_PULL_GPIO2_OFFSET 0x90
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#define RK3562_PULL_GPIO3_OFFSET 0x100A0
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#define RK3562_PULL_GPIO4_OFFSET 0x100B0
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static void rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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switch (bank->bank_num) {
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case 0:
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*reg = RK3562_PULL_GPIO0_OFFSET;
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break;
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case 1:
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*reg = RK3562_PULL_GPIO1_OFFSET;
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break;
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case 2:
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*reg = RK3562_PULL_GPIO2_OFFSET;
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break;
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case 3:
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*reg = RK3562_PULL_GPIO3_OFFSET;
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break;
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case 4:
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*reg = RK3562_PULL_GPIO4_OFFSET;
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break;
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default:
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*reg = 0;
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dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
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break;
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}
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*reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4);
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*bit = pin_num % RK3562_PULL_PINS_PER_REG;
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*bit *= RK3562_PULL_BITS_PER_PIN;
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}
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static int rk3562_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -ENOTSUPP;
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rk3562_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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type = bank->pull_type[pin_num / 8];
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3562_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3562_SMT_BITS_PER_PIN 2
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#define RK3562_SMT_PINS_PER_REG 8
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#define RK3562_SMT_GPIO0_OFFSET 0x20030
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#define RK3562_SMT_GPIO1_OFFSET 0xC0
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#define RK3562_SMT_GPIO2_OFFSET 0xD0
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#define RK3562_SMT_GPIO3_OFFSET 0x100E0
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#define RK3562_SMT_GPIO4_OFFSET 0x100F0
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static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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switch (bank->bank_num) {
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case 0:
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*reg = RK3562_SMT_GPIO0_OFFSET;
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break;
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case 1:
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*reg = RK3562_SMT_GPIO1_OFFSET;
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break;
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case 2:
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*reg = RK3562_SMT_GPIO2_OFFSET;
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break;
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case 3:
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*reg = RK3562_SMT_GPIO3_OFFSET;
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break;
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case 4:
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*reg = RK3562_SMT_GPIO4_OFFSET;
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break;
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default:
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*reg = 0;
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dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
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break;
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}
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*reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4);
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*bit = pin_num % RK3562_SMT_PINS_PER_REG;
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*bit *= RK3562_SMT_BITS_PER_PIN;
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return 0;
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}
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static int rk3562_set_schmitt(struct rockchip_pin_bank *bank,
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int pin_num, int enable)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data;
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u8 bit;
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rk3562_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3562_SMT_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (enable << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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static struct rockchip_pin_bank rk3562_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x20000, 0x20008, 0x20010, 0x20018),
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PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0, 0x08, 0x10, 0x18),
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PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x20, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x10040, 0x10048, 0x10050, 0x10058),
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PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0,
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0,
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0x10060, 0x10068, 0, 0),
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};
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static const struct rockchip_pin_ctrl rk3562_pin_ctrl = {
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.pin_banks = rk3562_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3562_pin_banks),
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.nr_pins = 144,
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.grf_mux_offset = 0x0,
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.set_mux = rk3562_set_mux,
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.set_pull = rk3562_set_pull,
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.set_drive = rk3562_set_drive,
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.set_schmitt = rk3562_set_schmitt,
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};
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static const struct udevice_id rk3562_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3562-pinctrl",
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.data = (ulong)&rk3562_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3562) = {
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.name = "rockchip_rk3562_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3562_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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