/*
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* SPROM format definitions for the Broadcom 47xx and 43xx chip family.
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* Broadcom Proprietary and Confidential. Copyright (C) 2020,
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* All Rights Reserved.
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*
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* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
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* the contents of this file may not be disclosed to third parties,
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* copied or duplicated in any form, in whole or in part, without
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* the prior written permission of Broadcom.
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*
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*
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* <<Broadcom-WL-IPTag/Proprietary:>>
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*/
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#ifndef _SBSPROM_H
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#define _SBSPROM_H
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#include "typedefs.h"
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#include "bcmdevs.h"
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/* A word is this many bytes */
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#define SRW 2
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/* offset into PCI config space for write enable bit */
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#define CFG_SROM_WRITABLE_OFFSET 0x88
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#define SROM_WRITEABLE 0x10
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/* enumeration space consists of N contiguous 4Kbyte core register sets */
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#define SBCORES_BASE 0x18000000
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#define SBCORES_EACH 0x1000
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/* offset from BAR0 for srom space */
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#define SROM_BASE 4096
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/* number of 2-byte words in srom */
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#define SROM_SIZE 64
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#define SROM_BYTES (SROM_SIZE * SRW)
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#define MAX_FN 4
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/* Word 0, Hardware control */
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#define SROM_HWCTL 0
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#define HW_FUNMSK 0x000f
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#define HW_FCLK 0x0200
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#define HW_CBM 0x0400
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#define HW_PIMSK 0xf000
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#define HW_PISHIFT 12
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#define HW_PI4402 0x2
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#define HW_FUN4401 0x0001
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#define HW_FCLK4402 0x0000
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/* Word 1, common-power/boot-rom */
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#define SROM_COMMPW 1
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/* boot rom present bit */
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#define BR_PRESSHIFT 8
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/* 15:9 for n; boot rom size is 2^(14 + n) bytes */
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#define BR_SIZESHIFT 9
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/* Word 2, SubsystemId */
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#define SROM_SSID 2
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/* Word 3, VendorId */
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#define SROM_VID 3
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/* Function 0 info, function info length */
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#define SROM_FN0 4
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#define SROM_FNSZ 8
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/* Within each function: */
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/* Word 0, deviceID */
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#define SRFN_DID 0
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/* Words 1-2, ClassCode */
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#define SRFN_CCL 1
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/* Word 2, D0 Power */
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#define SRFN_CCHD0 2
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/* Word 3, PME and D1D2D3 power */
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#define SRFN_PMED123 3
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#define PME_IL 0
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#define PME_ENET0 1
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#define PME_ENET1 2
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#define PME_CODEC 3
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#define PME_4402_ENET 0
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#define PME_4402_CODEC 1
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#define PMEREP_4402_ENET (PMERD3CV | PMERD3CA | PMERD3H | PMERD2 | PMERD1 | PMERD0 | PME)
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/* Word 4, Bar1 enable, pme reports */
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#define SRFN_B1PMER 4
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#define B1E 1
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#define B1SZMSK 0xe
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#define B1SZSH 1
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#define PMERMSK 0x0ff0
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#define PME 0x0010
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#define PMERD0 0x0020
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#define PMERD1 0x0040
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#define PMERD2 0x0080
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#define PMERD3H 0x0100
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#define PMERD3CA 0x0200
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#define PMERD3CV 0x0400
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#define IGNCLKRR 0x0800
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#define B0LMSK 0xf000
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/* Words 4-5, Bar0 Sonics value */
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#define SRFN_B0H 5
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/* Words 6-7, CIS Pointer */
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#define SRFN_CISL 6
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#define SRFN_CISH 7
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/* Words 36-38: iLine MAC address */
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#define SROM_I_MACHI 36
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#define SROM_I_MACMID 37
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#define SROM_I_MACLO 38
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/* Words 36-38: wireless0 MAC address on 43xx */
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#define SROM_W0_MACHI 36
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#define SROM_W0_MACMID 37
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#define SROM_W0_MACLO 38
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/* Words 39-41: enet0 MAC address */
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#define SROM_E0_MACHI 39
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#define SROM_E0_MACMID 40
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#define SROM_E0_MACLO 41
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/* Words 42-44: enet1 MAC address */
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#define SROM_E1_MACHI 42
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#define SROM_E1_MACMID 43
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#define SROM_E1_MACLO 44
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#define SROM_EPHY 45
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/* Words 47-51 wl0 PA bx */
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#define SROM_WL0_PAB0 47
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#define SROM_WL0_PAB1 48
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#define SROM_WL0_PAB2 49
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#define SROM_WL0_PAB3 50
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#define SROM_WL0_PAB4 51
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/* Word 52: wl0/wl1 MaxPower */
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#define SROM_WL_MAXPWR 52
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/* Words 53-55 wl1 PA bx */
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#define SROM_WL1_PAB0 53
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#define SROM_WL1_PAB1 54
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#define SROM_WL1_PAB2 55
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/* Woprd 56: itt */
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#define SROM_ITT 56
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/* Words 59-62: OEM Space */
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#define SROM_WL_OEM 59
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#define SROM_OEM_SIZE 4
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/* Contents for the srom */
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#define BU4710_SSID 0x0400
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#define VSIM4710_SSID 0x0401
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#define QT4710_SSID 0x0402
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#define BU4610_SSID 0x0403
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#define VSIM4610_SSID 0x0404
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#define BU4402_SSID 0x4402
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#define CLASS_OTHER 0x8000
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#define CLASS_ETHER 0x0000
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#define CLASS_NET 0x0002
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#define CLASS_COMM 0x0007
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#define CLASS_MODEM 0x0300
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#define CLASS_MIPS 0x3000
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#define CLASS_PROC 0x000b
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#define CLASS_FLASH 0x0100
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#define CLASS_MEM 0x0005
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#define CLASS_SERIALBUS 0x000c
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#define CLASS_OHCI 0x0310
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/* Broadcom IEEE MAC addresses are 00:90:4c:xx:xx:xx */
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#define MACHI 0x90
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#define MACMID_BU4710I 0x4c17
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#define MACMID_BU4710E0 0x4c18
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#define MACMID_BU4710E1 0x4c19
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#define MACMID_94710R1I 0x4c1a
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#define MACMID_94710R1E0 0x4c1b
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#define MACMID_94710R1E1 0x4c1c
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#define MACMID_94710R4I 0x4c1d
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#define MACMID_94710R4E0 0x4c1e
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#define MACMID_94710R4E1 0x4c1f
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#define MACMID_94710DEVI 0x4c20
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#define MACMID_94710DEVE0 0x4c21
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#define MACMID_94710DEVE1 0x4c22
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#define MACMID_BU4402 0x4c23
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#define MACMID_BU4610I 0x4c24
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#define MACMID_BU4610E0 0x4c25
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#define MACMID_BU4610E1 0x4c26
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#define MACMID_BU4401 0x4c37
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/* Enet phy settings one or two singles or a dual */
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/* Bits 4-0 : MII address for enet0 (0x1f for not there */
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/* Bits 9-5 : MII address for enet1 (0x1f for not there */
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/* Bit 14 : Mdio for enet0 */
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/* Bit 15 : Mdio for enet1 */
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/* bu4710 with only one phy on enet1 with address 7: */
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#define SROM_EPHY_ONE 0x80ff
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/* bu4710 with two individual phys, at 6 and 7, */
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/* each mdio connected to its own mac: */
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#define SROM_EPHY_TWO 0x80e6
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/* bu4710 with a dual phy addresses 0 & 1, mdio-connected to enet0 */
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/* bringup board has phyaddr0 and phyaddr1 swapped */
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#define SROM_EPHY_DUAL 0x0001
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/* r1 board with a dual phy at 0, 1 (NOT swapped and mdc0 */
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#define SROM_EPHY_R1 0x0010
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/* r4 board with a single phy on enet0 at address 5 and a switch */
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/* chip on enet1 (speciall case: 0x1e */
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#define SROM_EPHY_R4 0x83e5
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/* 4402 uses an internal phy at phyaddr 1; want mdcport == coreunit == 0 */
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#define SROM_EPHY_INTERNAL 0x0001
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#define SROM_VERS 0x0001
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#endif /* _SBSPROM_H */
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