/*
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* Broadcom PCIE
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* Software-specific definitions shared between device and host side
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* Explains the shared area between host and dongle
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*
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* Copyright (C) 2020, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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*
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* <<Broadcom-WL-IPTag/Dual:>>
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*/
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#ifndef _bcmpcie_h_
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#define _bcmpcie_h_
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#include <typedefs.h>
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#define ADDR_64(x) (x.addr)
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#define HIGH_ADDR_32(x) ((uint32) (((sh_addr_t) x).high_addr))
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#define LOW_ADDR_32(x) ((uint32) (((sh_addr_t) x).low_addr))
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typedef struct {
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uint32 low_addr;
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uint32 high_addr;
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} sh_addr_t;
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/* May be overridden by 43xxxxx-roml.mk */
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#if !defined(BCMPCIE_MAX_TX_FLOWS)
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#define BCMPCIE_MAX_TX_FLOWS 40
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#endif /* ! BCMPCIE_MAX_TX_FLOWS */
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#define PCIE_SHARED_VERSION_9 0x00009
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#define PCIE_SHARED_VERSION_8 0x00008
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#define PCIE_SHARED_VERSION_7 0x00007
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#define PCIE_SHARED_VERSION_6 0x00006 /* rev6 is compatible with rev 5 */
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#define PCIE_SHARED_VERSION_5 0x00005 /* rev6 is compatible with rev 5 */
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/**
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* Feature flags enabled in dongle. Advertised by dongle to DHD via the PCIe Shared structure that
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* is located in device memory.
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*/
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#define PCIE_SHARED_VERSION_MASK 0x000FF
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#define PCIE_SHARED_ASSERT_BUILT 0x00100
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#define PCIE_SHARED_ASSERT 0x00200
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#define PCIE_SHARED_TRAP 0x00400
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#define PCIE_SHARED_IN_BRPT 0x00800
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#define PCIE_SHARED_SET_BRPT 0x01000
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#define PCIE_SHARED_PENDING_BRPT 0x02000
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/* BCMPCIE_SUPPORT_TX_PUSH_RING 0x04000 obsolete */
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#define PCIE_SHARED_EVT_SEQNUM 0x08000
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#define PCIE_SHARED_DMA_INDEX 0x10000
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/**
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* There are host types where a device interrupt can 'race ahead' of data written by the device into
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* host memory. The dongle can avoid this condition using a variety of techniques (read barrier,
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* using PCIe Message Signalled Interrupts, or by using the PCIE_DMA_INDEX feature). Unfortunately
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* these techniques have drawbacks on router platforms. For these platforms, it was decided to not
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* avoid the condition, but to detect the condition instead and act on it.
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* D2H M2M DMA Complete Sync mechanism: Modulo-253-SeqNum or XORCSUM
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*/
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#define PCIE_SHARED_D2H_SYNC_SEQNUM 0x20000
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#define PCIE_SHARED_D2H_SYNC_XORCSUM 0x40000
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#define PCIE_SHARED_D2H_SYNC_MODE_MASK \
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(PCIE_SHARED_D2H_SYNC_SEQNUM | PCIE_SHARED_D2H_SYNC_XORCSUM)
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#define PCIE_SHARED_IDLE_FLOW_RING 0x80000
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#define PCIE_SHARED_2BYTE_INDICES 0x100000
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#define PCIE_SHARED_FAST_DELETE_RING 0x00000020 /* Fast Delete Ring */
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#define PCIE_SHARED_EVENT_BUF_POOL_MAX 0x000000c0 /* event buffer pool max bits */
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#define PCIE_SHARED_EVENT_BUF_POOL_MAX_POS 6 /* event buffer pool max bit position */
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/* dongle supports fatal buf log collection */
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#define PCIE_SHARED_FATAL_LOGBUG_VALID 0x200000
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/* Implicit DMA with corerev 19 and after */
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#define PCIE_SHARED_IDMA 0x400000
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/* MSI support */
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#define PCIE_SHARED_D2H_MSI_MULTI_MSG 0x800000
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/* IFRM with corerev 19 and after */
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#define PCIE_SHARED_IFRM 0x1000000
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/**
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* From Rev6 and above, suspend/resume can be done using two handshake methods.
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* 1. Using ctrl post/ctrl cmpl messages (Default rev6)
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* 2. Using Mailbox data (old method as used in rev5)
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* This shared flag indicates whether to overide rev6 default method and use mailbox for
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* suspend/resume.
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*/
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#define PCIE_SHARED_USE_MAILBOX 0x2000000
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/* Firmware compiled for mfgbuild purposes */
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#define PCIE_SHARED_MFGBUILD_FW 0x4000000
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/* Firmware could use DB0 value as host timestamp */
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#define PCIE_SHARED_TIMESTAMP_DB0 0x8000000
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/* Firmware could use Hostready (IPC rev7) */
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#define PCIE_SHARED_HOSTRDY_SUPPORT 0x10000000
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/* When set, Firmwar does not support OOB Device Wake based DS protocol */
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#define PCIE_SHARED_NO_OOB_DW 0x20000000
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/* When set, Firmwar supports Inband DS protocol */
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#define PCIE_SHARED_INBAND_DS 0x40000000
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/* use DAR registers */
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#define PCIE_SHARED_DAR 0x80000000
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/**
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* Following are the shared2 flags. All bits in flags have been used. A flags2
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* field got added and the definition for these flags come here:
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*/
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/* WAR: D11 txstatus through unused status field of PCIe completion header */
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#define PCIE_SHARED2_EXTENDED_TRAP_DATA 0x00000001 /* using flags2 in shared area */
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#define PCIE_SHARED2_TXSTATUS_METADATA 0x00000002
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#define PCIE_SHARED2_BT_LOGGING 0x00000004 /* BT logging support */
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#define PCIE_SHARED2_SNAPSHOT_UPLOAD 0x00000008 /* BT/WLAN snapshot upload support */
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#define PCIE_SHARED2_SUBMIT_COUNT_WAR 0x00000010 /* submission count WAR */
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#define PCIE_SHARED2_FAST_DELETE_RING 0x00000020 /* Fast Delete ring support */
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#define PCIE_SHARED2_EVTBUF_MAX_MASK 0x000000C0 /* 0:32, 1:64, 2:128, 3: 256 */
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/* using flags2 to indicate firmware support added to reuse timesync to update PKT txstatus */
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#define PCIE_SHARED2_PKT_TX_STATUS 0x00000100
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#define PCIE_SHARED2_FW_SMALL_MEMDUMP 0x00000200 /* FW small memdump */
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#define PCIE_SHARED2_FW_HC_ON_TRAP 0x00000400
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#define PCIE_SHARED2_HSCB 0x00000800 /* Host SCB support */
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#define PCIE_SHARED2_EDL_RING 0x00001000 /* Support Enhanced Debug Lane */
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#define PCIE_SHARED2_DEBUG_BUF_DEST 0x00002000 /* debug buf dest support */
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#define PCIE_SHARED2_PCIE_ENUM_RESET_FLR 0x00004000 /* BT producer index reset WAR */
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#define PCIE_SHARED2_PKT_TIMESTAMP 0x00008000 /* Timestamp in packet */
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#define PCIE_SHARED2_HP2P 0x00010000u /* HP2P feature */
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#define PCIE_SHARED2_HWA 0x00020000u /* HWA feature */
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#define PCIE_SHARED2_TRAP_ON_HOST_DB7 0x00040000u /* can take a trap on DB7 from host */
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#define PCIE_SHARED2_DURATION_SCALE 0x00100000u
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#define PCIE_SHARED2_ETD_ADDR_SUPPORT 0x00800000u
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#define PCIE_SHARED2_TXCSO 0x00200000u /* Tx Checksum offload support */
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#define PCIE_SHARED2_TXPOST_EXT 0x00400000u /* extended txpost work item support */
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#define PCIE_SHARED2_D2H_D11_TX_STATUS 0x40000000
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#define PCIE_SHARED2_H2D_D11_TX_STATUS 0x80000000
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#define PCIE_SHARED_D2H_MAGIC 0xFEDCBA09
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#define PCIE_SHARED_H2D_MAGIC 0x12345678
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typedef uint16 pcie_hwa_db_index_t; /* 16 bit HWA index (IPC Rev 7) */
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#define PCIE_HWA_DB_INDEX_SZ (2u) /* 2 bytes sizeof(pcie_hwa_db_index_t) */
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/**
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* Message rings convey messages between host and device. They are unidirectional, and are located
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* in host memory.
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*
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* This is the minimal set of message rings, known as 'common message rings':
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*/
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#define BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT 0
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#define BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT 1
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#define BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE 2
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#define BCMPCIE_D2H_MSGRING_TX_COMPLETE 3
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#define BCMPCIE_D2H_MSGRING_RX_COMPLETE 4
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#define BCMPCIE_COMMON_MSGRING_MAX_ID 4
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#define BCMPCIE_H2D_COMMON_MSGRINGS 2
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#define BCMPCIE_D2H_COMMON_MSGRINGS 3
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#define BCMPCIE_COMMON_MSGRINGS 5
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#define BCMPCIE_H2D_MSGRINGS(max_tx_flows) \
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(BCMPCIE_H2D_COMMON_MSGRINGS + (max_tx_flows))
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/* different ring types */
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#define BCMPCIE_H2D_RING_TYPE_CTRL_SUBMIT 0x1
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#define BCMPCIE_H2D_RING_TYPE_TXFLOW_RING 0x2
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#define BCMPCIE_H2D_RING_TYPE_RXBUFPOST 0x3
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#define BCMPCIE_H2D_RING_TYPE_TXSUBMIT 0x4
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#define BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT 0x5
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#define BCMPCIE_H2D_RING_TYPE_BTLOG_SUBMIT 0x6
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#define BCMPCIE_D2H_RING_TYPE_CTRL_CPL 0x1
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#define BCMPCIE_D2H_RING_TYPE_TX_CPL 0x2
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#define BCMPCIE_D2H_RING_TYPE_RX_CPL 0x3
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#define BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL 0x4
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#define BCMPCIE_D2H_RING_TYPE_AC_RX_COMPLETE 0x5
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#define BCMPCIE_D2H_RING_TYPE_BTLOG_CPL 0x6
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#define BCMPCIE_D2H_RING_TYPE_EDL 0x7
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#define BCMPCIE_D2H_RING_TYPE_HPP_TX_CPL 0x8
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#define BCMPCIE_D2H_RING_TYPE_HPP_RX_CPL 0x9
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/**
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* H2D and D2H, WR and RD index, are maintained in the following arrays:
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* - Array of all H2D WR Indices
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* - Array of all H2D RD Indices
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* - Array of all D2H WR Indices
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* - Array of all D2H RD Indices
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*
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* The offset of the WR or RD indexes (for common rings) in these arrays are
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* listed below. Arrays ARE NOT indexed by a ring's id.
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*
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* D2H common rings WR and RD index start from 0, even though their ringids
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* start from BCMPCIE_H2D_COMMON_MSGRINGS
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*/
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#define BCMPCIE_H2D_RING_IDX(h2d_ring_id) (h2d_ring_id)
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enum h2dring_idx {
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/* H2D common rings */
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BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT_IDX =
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BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT),
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BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT_IDX =
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BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT),
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/* First TxPost's WR or RD index starts after all H2D common rings */
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BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START =
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BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_COMMON_MSGRINGS)
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};
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#define BCMPCIE_D2H_RING_IDX(d2h_ring_id) \
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((d2h_ring_id) - BCMPCIE_H2D_COMMON_MSGRINGS)
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enum d2hring_idx {
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/* D2H Common Rings */
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BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE_IDX =
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BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE),
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BCMPCIE_D2H_MSGRING_TX_COMPLETE_IDX =
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BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_TX_COMPLETE),
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BCMPCIE_D2H_MSGRING_RX_COMPLETE_IDX =
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BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_RX_COMPLETE)
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};
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/**
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* Macros for managing arrays of RD WR indices:
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* rw_index_sz:
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* - in dongle, rw_index_sz is known at compile time
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* - in host/DHD, rw_index_sz is derived from advertized pci_shared flags
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*
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* ring_idx: See h2dring_idx and d2hring_idx
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*/
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/** Offset of a RD or WR index in H2D or D2H indices array */
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#define BCMPCIE_RW_INDEX_OFFSET(rw_index_sz, ring_idx) \
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((rw_index_sz) * (ring_idx))
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/** Fetch the address of RD or WR index in H2D or D2H indices array */
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#define BCMPCIE_RW_INDEX_ADDR(indices_array_base, rw_index_sz, ring_idx) \
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(void *)((uint32)(indices_array_base) + \
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BCMPCIE_RW_INDEX_OFFSET((rw_index_sz), (ring_idx)))
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/** H2D DMA Indices array size: given max flow rings */
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#define BCMPCIE_H2D_RW_INDEX_ARRAY_SZ(rw_index_sz, max_tx_flows) \
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((rw_index_sz) * BCMPCIE_H2D_MSGRINGS(max_tx_flows))
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/** D2H DMA Indices array size */
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#define BCMPCIE_D2H_RW_INDEX_ARRAY_SZ(rw_index_sz) \
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((rw_index_sz) * BCMPCIE_D2H_COMMON_MSGRINGS)
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/* Backwards compatibility for legacy branches. */
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#if !defined(PHYS_ADDR_N)
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#define PHYS_ADDR_N(name) name
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#endif
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/**
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* This type is used by a 'message buffer' (which is a FIFO for messages). Message buffers are used
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* for host<->device communication and are instantiated on both sides. ring_mem_t is instantiated
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* both in host as well as device memory.
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*/
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typedef struct ring_mem {
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uint16 idx; /* ring id */
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uint8 type;
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uint8 rsvd;
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uint16 max_item; /* Max number of items in flow ring */
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uint16 len_items; /* Items are fixed size. Length in bytes of one item */
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sh_addr_t base_addr; /* 64 bits address, either in host or device memory */
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} ring_mem_t;
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/**
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* Per flow ring, information is maintained in device memory, eg at what address the ringmem and
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* ringstate are located. The flow ring itself can be instantiated in either host or device memory.
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*
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* Perhaps this type should be renamed to make clear that it resides in device memory only.
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*/
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typedef struct ring_info {
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uint32 PHYS_ADDR_N(ringmem_ptr); /* ring mem location in dongle memory */
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/* Following arrays are indexed using h2dring_idx and d2hring_idx, and not
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* by a ringid.
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*/
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/* 32bit ptr to arrays of WR or RD indices for all rings in dongle memory */
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uint32 PHYS_ADDR_N(h2d_w_idx_ptr); /* Array of all H2D ring's WR indices */
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uint32 PHYS_ADDR_N(h2d_r_idx_ptr); /* Array of all H2D ring's RD indices */
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uint32 PHYS_ADDR_N(d2h_w_idx_ptr); /* Array of all D2H ring's WR indices */
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uint32 PHYS_ADDR_N(d2h_r_idx_ptr); /* Array of all D2H ring's RD indices */
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/* PCIE_DMA_INDEX feature: Dongle uses mem2mem DMA to sync arrays in host.
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* Host may directly fetch WR and RD indices from these host-side arrays.
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*
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* 64bit ptr to arrays of WR or RD indices for all rings in host memory.
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*/
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sh_addr_t h2d_w_idx_hostaddr; /* Array of all H2D ring's WR indices */
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sh_addr_t h2d_r_idx_hostaddr; /* Array of all H2D ring's RD indices */
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sh_addr_t d2h_w_idx_hostaddr; /* Array of all D2H ring's WR indices */
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sh_addr_t d2h_r_idx_hostaddr; /* Array of all D2H ring's RD indices */
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uint16 max_tx_flowrings; /* maximum number of H2D rings: common + flow */
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uint16 max_submission_queues; /* maximum number of H2D rings: common + flow */
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uint16 max_completion_rings; /* maximum number of H2D rings: common + flow */
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uint16 max_vdevs; /* max number of virtual interfaces supported */
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sh_addr_t ifrm_w_idx_hostaddr; /* Array of all H2D ring's WR indices for IFRM */
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/* 32bit ptr to arrays of HWA DB indices for all rings in dongle memory */
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uint32 PHYS_ADDR_N(h2d_hwa_db_idx_ptr); /* Array of all H2D rings HWA DB indices */
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uint32 PHYS_ADDR_N(d2h_hwa_db_idx_ptr); /* Array of all D2H rings HWA DB indices */
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} ring_info_t;
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/**
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* A structure located in TCM that is shared between host and device, primarily used during
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* initialization.
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*/
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typedef struct {
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/** shared area version captured at flags 7:0 */
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uint32 flags;
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uint32 PHYS_ADDR_N(trap_addr);
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uint32 PHYS_ADDR_N(assert_exp_addr);
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uint32 PHYS_ADDR_N(assert_file_addr);
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uint32 assert_line;
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uint32 PHYS_ADDR_N(console_addr); /**< Address of hnd_cons_t */
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uint32 PHYS_ADDR_N(msgtrace_addr);
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uint32 fwid;
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/* Used for debug/flow control */
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uint16 total_lfrag_pkt_cnt;
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uint16 max_host_rxbufs; /* rsvd in spec */
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uint32 dma_rxoffset; /* rsvd in spec */
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/** these will be used for sleep request/ack, d3 req/ack */
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uint32 PHYS_ADDR_N(h2d_mb_data_ptr);
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uint32 PHYS_ADDR_N(d2h_mb_data_ptr);
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/* information pertinent to host IPC/msgbuf channels */
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/** location in the TCM memory which has the ring_info */
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uint32 PHYS_ADDR_N(rings_info_ptr);
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/** block of host memory for the scratch buffer */
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uint32 host_dma_scratch_buffer_len;
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sh_addr_t host_dma_scratch_buffer;
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/* location in host memory for scb host offload structures */
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sh_addr_t host_scb_addr;
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uint32 host_scb_size;
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/* anonymous union for overloading fields in structure */
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union {
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uint32 buzz_dbg_ptr; /* BUZZZ state format strings and trace buffer */
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struct {
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/* Host provided trap buffer length in words */
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uint16 device_trap_debug_buffer_len;
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uint16 rsvd2;
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};
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};
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/* rev6 compatible changes */
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uint32 flags2;
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uint32 host_cap;
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/* location in the host address space to write trap indication.
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* At this point for the current rev of the spec, firmware will
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* support only indications to 32 bit host addresses.
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* This essentially is device_trap_debug_buffer_addr
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*/
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sh_addr_t host_trap_addr;
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/* location for host fatal error log buffer start address */
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uint32 PHYS_ADDR_N(device_fatal_logbuf_start);
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/* location in host memory for offloaded modules */
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sh_addr_t hoffload_addr;
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uint32 flags3;
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uint32 host_cap2;
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uint32 host_cap3; /* host indicates its txpost ext tag capabilities */
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uint32 PHYS_ADDR_N(etd_addr);
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/* Device advertises the txpost extended tag capabilities */
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uint32 device_txpost_ext_tags_bitmask;
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} pciedev_shared_t;
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/* Device F/W provides the following access function:
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* pciedev_shared_t *hnd_get_pciedev_shared(void);
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*/
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/* host capabilities */
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#define HOSTCAP_PCIEAPI_VERSION_MASK 0x000000FF
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#define HOSTCAP_H2D_VALID_PHASE 0x00000100
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#define HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE 0x00000200
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#define HOSTCAP_H2D_ENABLE_HOSTRDY 0x00000400
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#define HOSTCAP_DB0_TIMESTAMP 0x00000800
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#define HOSTCAP_DS_NO_OOB_DW 0x00001000
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#define HOSTCAP_DS_INBAND_DW 0x00002000
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#define HOSTCAP_H2D_IDMA 0x00004000
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#define HOSTCAP_H2D_IFRM 0x00008000
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#define HOSTCAP_H2D_DAR 0x00010000
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#define HOSTCAP_EXTENDED_TRAP_DATA 0x00020000
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#define HOSTCAP_TXSTATUS_METADATA 0x00040000
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#define HOSTCAP_BT_LOGGING 0x00080000
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#define HOSTCAP_SNAPSHOT_UPLOAD 0x00100000
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#define HOSTCAP_FAST_DELETE_RING 0x00200000
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#define HOSTCAP_PKT_TXSTATUS 0x00400000
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#define HOSTCAP_UR_FW_NO_TRAP 0x00800000 /* Don't trap on UR */
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#define HOSTCAP_TX_CSO 0x01000000
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#define HOSTCAP_HSCB 0x02000000
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/* Host support for extended device trap debug buffer */
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#define HOSTCAP_EXT_TRAP_DBGBUF 0x04000000
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#define HOSTCAP_TXPOST_EXT 0x08000000
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/* Host support for enhanced debug lane */
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#define HOSTCAP_EDL_RING 0x10000000
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#define HOSTCAP_PKT_TIMESTAMP 0x20000000
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#define HOSTCAP_PKT_HP2P 0x40000000
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#define HOSTCAP_HWA 0x80000000
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#define HOSTCAP2_DURATION_SCALE_MASK 0x0000003Fu
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/* extended trap debug buffer allocation sizes. Note that this buffer can be used for
|
* other trap related purposes also.
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*/
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#define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MIN (64u * 1024u)
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#define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN (96u * 1024u)
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#define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MAX (256u * 1024u)
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/**
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* Mailboxes notify a remote party that an event took place, using interrupts. They use hardware
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* support.
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*/
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/* H2D mail box Data */
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#define H2D_HOST_D3_INFORM 0x00000001
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#define H2D_HOST_DS_ACK 0x00000002
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#define H2D_HOST_DS_NAK 0x00000004
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#define H2D_HOST_D0_INFORM_IN_USE 0x00000008
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#define H2D_HOST_D0_INFORM 0x00000010
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#define H2DMB_DS_ACTIVE 0x00000020
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#define H2DMB_DS_DEVICE_WAKE 0x00000040
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#define H2D_HOST_IDMA_INITED 0x00000080
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#define H2D_HOST_ACK_NOINT 0x00010000 /* d2h_ack interrupt ignore */
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#define H2D_HOST_CONS_INT 0x80000000 /**< h2d int for console cmds */
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#define H2D_FW_TRAP 0x20000000 /**< h2d force TRAP */
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#define H2DMB_DS_HOST_SLEEP_INFORM H2D_HOST_D3_INFORM
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#define H2DMB_DS_DEVICE_SLEEP_ACK H2D_HOST_DS_ACK
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#define H2DMB_DS_DEVICE_SLEEP_NAK H2D_HOST_DS_NAK
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#define H2DMB_D0_INFORM_IN_USE H2D_HOST_D0_INFORM_IN_USE
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#define H2DMB_D0_INFORM H2D_HOST_D0_INFORM
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#define H2DMB_FW_TRAP H2D_FW_TRAP
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#define H2DMB_HOST_CONS_INT H2D_HOST_CONS_INT
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#define H2DMB_DS_DEVICE_WAKE_ASSERT H2DMB_DS_DEVICE_WAKE
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#define H2DMB_DS_DEVICE_WAKE_DEASSERT H2DMB_DS_ACTIVE
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/* D2H mail box Data */
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#define D2H_DEV_D3_ACK 0x00000001
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#define D2H_DEV_DS_ENTER_REQ 0x00000002
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#define D2H_DEV_DS_EXIT_NOTE 0x00000004
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#define D2HMB_DS_HOST_SLEEP_EXIT_ACK 0x00000008
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#define D2H_DEV_IDMA_INITED 0x00000010
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#define D2HMB_DS_HOST_SLEEP_ACK D2H_DEV_D3_ACK
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#define D2HMB_DS_DEVICE_SLEEP_ENTER_REQ D2H_DEV_DS_ENTER_REQ
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#define D2HMB_DS_DEVICE_SLEEP_EXIT D2H_DEV_DS_EXIT_NOTE
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#define D2H_DEV_MB_MASK (D2H_DEV_D3_ACK | D2H_DEV_DS_ENTER_REQ | \
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D2H_DEV_DS_EXIT_NOTE | D2H_DEV_IDMA_INITED)
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#define D2H_DEV_MB_INVALIDATED(x) ((!x) || (x & ~D2H_DEV_MB_MASK))
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/* trap data codes */
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#define D2H_DEV_FWHALT 0x10000000
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#define D2H_DEV_EXT_TRAP_DATA 0x20000000
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#define D2H_DEV_TRAP_IN_TRAP 0x40000000
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#define D2H_DEV_TRAP_HOSTDB 0x80000000 /* trap as set by host DB */
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#define D2H_DEV_TRAP_DUE_TO_BT 0x01000000
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/* Indicates trap due to HMAP violation */
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#define D2H_DEV_TRAP_DUE_TO_HMAP 0x02000000
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/* Indicates whether HMAP violation was Write */
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#define D2H_DEV_TRAP_HMAP_WRITE 0x04000000
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#define D2H_DEV_TRAP_PING_HOST_FAILURE 0x08000000
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#define D2H_FWTRAP_MASK 0x0000001F /* Adding maskbits for TRAP information */
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#define D2HMB_FWHALT D2H_DEV_FWHALT
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#define D2HMB_TRAP_IN_TRAP D2H_DEV_TRAP_IN_TRAP
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#define D2HMB_EXT_TRAP_DATA D2H_DEV_EXT_TRAP_DATA
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#define D2H_FWTRAP_MAC_SSSR_RDY 0x00010000u /* MAC SSSR prepped */
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/* Size of Extended Trap data Buffer */
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#define BCMPCIE_EXT_TRAP_DATA_MAXLEN 4096
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/** These macro's operate on type 'inuse_lclbuf_pool_t' and are used by firmware only */
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#define PREVTXP(i, d) (((i) == 0) ? ((d) - 1) : ((i) - 1))
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#define NEXTTXP(i, d) ((((i)+1) >= (d)) ? 0 : ((i)+1))
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#define NEXTNTXP(i, n, d) ((((i)+(n)) >= (d)) ? 0 : ((i)+(n)))
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#define NTXPACTIVE(r, w, d) (((r) <= (w)) ? ((w)-(r)) : ((d)-(r)+(w)))
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#define NTXPAVAIL(r, w, d) (((d) - NTXPACTIVE((r), (w), (d))) > 1)
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/* Function can be used to notify host of FW halt */
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#define READ_AVAIL_SPACE(w, r, d) ((w >= r) ? (uint32)(w - r) : (uint32)(d - r))
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#define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d) ((w >= r) ? (d - w) : (r - w))
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#define WRITE_SPACE_AVAIL(r, w, d) (d - (NTXPACTIVE(r, w, d)) - 1)
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#define CHECK_WRITE_SPACE(r, w, d) ((r) > (w)) ? \
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(uint32)((r) - (w) - 1) : ((r) == 0 || (w) == 0) ? \
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(uint32)((d) - (w) - 1) : (uint32)((d) - (w))
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#define CHECK_NOWRITE_SPACE(r, w, d) \
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(((uint32)(r) == (uint32)((w) + 1)) || (((r) == 0) && ((w) == ((d) - 1))))
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/* These should be moved into pciedev.h --- */
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#define WRT_PEND(x) ((x)->wr_pending)
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#define DNGL_RING_WPTR(msgbuf) (*((msgbuf)->tcm_rs_w_ptr)) /**< advanced by producer */
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#define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a) (DNGL_RING_WPTR(msgbuf) = (a))
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#define DNGL_RING_RPTR(msgbuf) (*((msgbuf)->tcm_rs_r_ptr)) /**< advanced by consumer */
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#define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a) (DNGL_RING_RPTR(msgbuf) = (a))
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#define MODULO_RING_IDX(x, y) ((x) % (y)->bitmap_size)
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#define RING_READ_PTR(x) ((x)->ringstate->r_offset)
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#define RING_WRITE_PTR(x) ((x)->ringstate->w_offset)
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#define RING_START_PTR(x) ((x)->ringmem->base_addr.low_addr)
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#define RING_MAX_ITEM(x) ((x)->ringmem->max_item)
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#define RING_LEN_ITEMS(x) ((x)->ringmem->len_items)
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#define HOST_RING_BASE(x) ((x)->dma_buf.va)
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#define HOST_RING_END(x) ((uint8 *)HOST_RING_BASE((x)) + \
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((RING_MAX_ITEM((x))-1)*RING_LEN_ITEMS((x))))
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/* Trap types copied in the pciedev_shared.trap_addr */
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#define FW_INITIATED_TRAP_TYPE (0x1 << 7)
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#define HEALTHCHECK_NODS_TRAP_TYPE (0x1 << 6)
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/* Device supported txpost extended tag capabilities */
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#define PCIE_SHARED2_DEV_TXPOST_EXT_TAG_CAP_RSVD (1u << 0u) /* Reserved */
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#define PCIE_SHARED2_DEV_TXPOST_EXT_TAG_CAP_CSO (1u << 1u) /* CSO */
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#define PCIE_SHARED2_DEV_TXPOST_EXT_TAG_CAP_MESH (1u << 2u) /* MESH */
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#define RING_MESH(x) (((x)->txpost_ext_cap_flags) & PCIE_SHARED2_DEV_TXPOST_EXT_TAG_CAP_MESH)
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#endif /* _bcmpcie_h_ */
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