/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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/*@************************************************************
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* include files
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************************************************************/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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void phydm_start_cck_cont_tx_jgr3(void *dm_void,
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struct phydm_pmac_info *tx_info)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
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u8 rate = tx_info->tx_rate; /* HW rate */
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/* if CCK block on? */
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if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
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odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 0x1);
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if (dm->support_ic_type & ODM_RTL8723F) {
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odm_set_bb_reg(dm, R_0x2a08, BIT(21)|BIT(20), rate);
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odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/
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} else {
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/* Turn Off All Test mode */
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odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
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odm_set_bb_reg(dm, R_0x1a00, 0x3000, rate);
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odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* transmit mode */
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odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
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/* Fix rate selection issue */
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odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x1);
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/* set RX weighting for path I & Q to 0 */
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odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
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/* set loopback mode */
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odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x1);
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}
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pmac_tx->cck_cont_tx = true;
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pmac_tx->ofdm_cont_tx = false;
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}
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void phydm_stop_cck_cont_tx_jgr3(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
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pmac_tx->cck_cont_tx = false;
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pmac_tx->ofdm_cont_tx = false;
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if (dm->support_ic_type & ODM_RTL8723F) {
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/* @Disable pmac tx_en*/
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odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/
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} else {
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odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* normal mode */
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odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
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/* back to default */
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odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x0);
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odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
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odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x0);
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}
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/* BB Reset */
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odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
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odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
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}
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void phydm_start_ofdm_cont_tx_jgr3(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
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/* 1. if OFDM block on */
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if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
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odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 0x1);
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if (!(dm->support_ic_type & ODM_RTL8723F)) {
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/* 2. set CCK test mode off, set to CCK normal mode */
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odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
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/* 3. turn on scramble setting */
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odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
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}
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/* 4. Turn On Continue Tx and turn off the other test modes. */
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odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1);
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pmac_tx->cck_cont_tx = false;
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pmac_tx->ofdm_cont_tx = true;
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}
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void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
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pmac_tx->cck_cont_tx = false;
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pmac_tx->ofdm_cont_tx = false;
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/* Turn Off All Test mode */
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odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
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/* Delay 10 ms */
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ODM_delay_ms(10);
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/* BB Reset */
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odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
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odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
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}
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void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
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u32 tmp = 0;
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odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x2); /* TX Stop */
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if (dm->support_ic_type & ODM_RTL8723F) {
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if (tx_info->mode == CONT_TX) {
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if (pmac_tx->is_cck_rate) {
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/* TX Stop */
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odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
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/* Clear BB cont tx */
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odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
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/* Clear PMAC cont tx */
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odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
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/* Clear TX Stop */
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odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
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phydm_stop_cck_cont_tx_jgr3(dm);
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} else
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phydm_stop_ofdm_cont_tx_jgr3(dm);
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} else {
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if (pmac_tx->is_cck_rate) {
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/* packet_count = 0x1 */
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odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, 0x1);
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/* @Disable pmac tx_en*/
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odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
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/* @Enable pmac tx_en*/
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odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
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phydm_stop_cck_cont_tx_jgr3(dm);
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}
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}
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}else {
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if (tx_info->mode == CONT_TX) {
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if (pmac_tx->is_cck_rate)
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phydm_stop_cck_cont_tx_jgr3(dm);
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else
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phydm_stop_ofdm_cont_tx_jgr3(dm);
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}
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}
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}
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void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
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struct phydm_pmac_info *tx_info)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
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u32 tmp = 0;
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odm_set_bb_reg(dm, R_0xa58, 0x003f8000, tx_info->tx_rate);
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/*0x900[1] ndp_sound */
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odm_set_bb_reg(dm, R_0x900, BIT(1), tx_info->ndp_sound);
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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tx_info->m_stbc = tx_info->m_stbc - 1;
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#endif
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/*0x900[27:24] txsc [29:28] bw [31:30] m_stbc */
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tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
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((tx_info->m_stbc) << 6);
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odm_set_bb_reg(dm, R_0x900, 0xff000000, tmp);
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if (tx_info->tx_sc == 1) /*upper*/
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odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x5);
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else if (tx_info->tx_sc == 2) /*lower*/
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odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x6);
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else /* duplicate*/
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odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x0);
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if (pmac_tx->is_ht_rate) {
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odm_set_bb_reg(dm, R_0x900, BIT(0), 0x1);
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odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
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} else if (pmac_tx->is_vht_rate) {
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odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
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odm_set_bb_reg(dm, R_0x900, BIT(2), 0x1);
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} else {
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odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
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odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
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}
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/* for TX interval */
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odm_set_bb_reg(dm, R_0x9b8, MASKHWORD, tx_info->packet_period);
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}
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void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
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u32 tmp = 0;
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if (pmac_tx->is_cck_rate)
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return;
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odm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count);
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/* L-SIG */
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tmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1],
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tx_info->lsig[0]);
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odm_set_bb_reg(dm, R_0x908, 0xffffff, tmp);
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if (pmac_tx->is_ht_rate) {
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/* HT SIG */
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tmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1],
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tx_info->ht_sig[0]);
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odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
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tmp = BYTE_2_DWORD(0, tx_info->ht_sig[5], tx_info->ht_sig[4],
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tx_info->ht_sig[3]);
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odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
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} else if (pmac_tx->is_vht_rate) {
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/* VHT SIG A/B/serv_field/delimiter */
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tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2],
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tx_info->vht_sig_a[1],
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tx_info->vht_sig_a[0]);
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odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
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tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[5],
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tx_info->vht_sig_a[4],
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tx_info->vht_sig_a[3]);
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odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
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tmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2],
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tx_info->vht_sig_b[1],
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tx_info->vht_sig_b[0]);
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odm_set_bb_reg(dm, R_0x914, 0x1fffffff, tmp);
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odm_set_bb_reg(dm, R_0x938, 0xff00, tx_info->vht_sig_b_crc);
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tmp = BYTE_2_DWORD(tx_info->vht_delimiter[3],
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tx_info->vht_delimiter[2],
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tx_info->vht_delimiter[1],
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tx_info->vht_delimiter[0]);
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odm_set_bb_reg(dm, R_0x940, MASKDWORD, tmp);
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}
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}
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void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
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struct phydm_pmac_info *tx_info)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
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u32 tmp = 0;
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u8 rate = tx_info->tx_rate; /* HW rate */
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if (!pmac_tx->is_cck_rate)
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return;
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if (dm->support_ic_type & ODM_RTL8723F) {
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#if (RTL8723F_SUPPORT)
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odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, tx_info->packet_count);
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odm_set_bb_reg(dm, R_0x2a08, BIT(22), tx_info->service_field_bit2);
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odm_set_bb_reg(dm, R_0x2a08, BIT(21) | BIT(20), rate);
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odm_set_bb_reg(dm, R_0x2a08, 0x1ffff, tx_info->packet_length);
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/* turn on scrambler */
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odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);
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if (tx_info->is_short_preamble)
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odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x1);
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else
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odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x0);
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#endif
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} else {
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tmp = tx_info->packet_count | (tx_info->sfd << 16);
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odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp);
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tmp = tx_info->signal_field | (tx_info->service_field << 8) |
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(tx_info->length << 16);
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odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp);
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tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]);
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odm_set_bb_reg(dm, R_0x1e6c, MASKLWORD, tmp);
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if (tx_info->is_short_preamble)
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odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x0);
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else
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odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x1);
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}
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}
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void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
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enum phydm_pmac_mode mode)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
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if (mode == CONT_TX) {
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tx_info->packet_count = 1;
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if (pmac_tx->is_cck_rate)
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phydm_start_cck_cont_tx_jgr3(dm, tx_info);
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else
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phydm_start_ofdm_cont_tx_jgr3(dm);
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}
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}
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void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
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odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x1); /*Turn on PMAC */
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if (dm->support_ic_type & ODM_RTL8723F) {
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if (pmac_tx->is_cck_rate) {
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if (tx_info->mode == CONT_TX) {
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/* BB and PMAC cont tx */
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odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
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odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
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}
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/* TX CCK ON */
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odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
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odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
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} else {
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odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x0); /*TX Ofdm OFF */
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odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
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}
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} else {
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/*mac scramble seed setting, only in 8198F */
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#if (RTL8198F_SUPPORT)
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if (dm->support_ic_type & ODM_RTL8198F)
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if (!odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
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odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x1);
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#endif
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if (pmac_tx->is_cck_rate){
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odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x8); /*TX CCK ON */
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odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x0);
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} else {
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odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
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}
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}
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}
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void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
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enum rf_path mpt_rf_path)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
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pmac_tx->is_cck_rate = phydm_is_cck_rate(dm, tx_info->tx_rate);
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pmac_tx->is_ofdm_rate = phydm_is_ofdm_rate(dm, tx_info->tx_rate);
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pmac_tx->is_ht_rate = phydm_is_ht_rate(dm, tx_info->tx_rate);
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pmac_tx->is_vht_rate = phydm_is_vht_rate(dm, tx_info->tx_rate);
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pmac_tx->path = mpt_rf_path;
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if (!tx_info->en_pmac_tx) {
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phydm_stop_pmac_tx_jgr3(dm, tx_info);
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return;
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}
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phydm_set_mode_jgr3(dm, tx_info, tx_info->mode);
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if (pmac_tx->is_cck_rate)
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phydm_set_cck_preamble_hdr_jgr3(dm, tx_info);
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else
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phydm_set_sig_jgr3(dm, tx_info);
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phydm_set_mac_phy_txinfo_jgr3(dm, tx_info);
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phydm_set_pmac_txon_jgr3(dm, tx_info);
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}
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void phydm_set_tmac_tx_jgr3(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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/* Turn on TMAC */
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if (odm_get_bb_reg(dm, R_0x1d08, BIT(0)))
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odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x0);
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/* mac scramble seed setting, only in 8198F */
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#if (RTL8198F_SUPPORT)
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if (dm->support_ic_type & ODM_RTL8198F)
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if (odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
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odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x0);
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#endif
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/* Turn on TMAC CCK */
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if (!(dm->support_ic_type & ODM_RTL8723F)) {
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if (!odm_get_bb_reg(dm, R_0x1a84, BIT(31)))
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odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x1);
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}
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}
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#endif
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void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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phydm_start_cck_cont_tx_jgr3(dm, tx_info);
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#endif
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}
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void phydm_stop_cck_cont_tx(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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phydm_stop_cck_cont_tx_jgr3(dm);
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#endif
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}
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void phydm_start_ofdm_cont_tx(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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phydm_start_ofdm_cont_tx_jgr3(dm);
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#endif
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}
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void phydm_stop_ofdm_cont_tx(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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phydm_stop_ofdm_cont_tx_jgr3(dm);
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#endif
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}
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void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
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enum rf_path mpt_rf_path)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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phydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path);
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#endif
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}
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void phydm_set_tmac_tx(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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phydm_set_tmac_tx_jgr3(dm);
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#endif
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}
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void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pmac_info tx_info;
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char help[] = "-h";
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char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
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u32 var[10] = {0};
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u32 used = *_used;
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u32 out_len = *_out_len;
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u8 i = 0;
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u32 tx_cnt = 0x0;
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u8 poll_cnt = 0x0;
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PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
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if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
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return;
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if ((strcmp(input[1], help) == 0)) {
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PDM_SNPF(out_len, used, output + used, out_len - used,
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"[pmac_tx] basic : {1} {rate_idx}(only 1M & 6M) {count}\n");
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} else {
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for (i = 1; i < 7; i++) {
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if (input[i + 1]) {
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PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
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&var[i]);
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}
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}
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tx_info.en_pmac_tx = true;
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tx_info.mode = PKTS_TX;
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tx_info.ndp_sound = false;
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tx_info.bw = CHANNEL_WIDTH_20;
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tx_info.tx_sc = 0x0; /*duplicate*/
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tx_info.m_stbc = 0x0; /*disable*/
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tx_info.packet_period = 2000; /*d'500 us*/
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tx_info.tx_rate = (u8)var[1];
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tx_info.packet_count = (u32)var[2];
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if (tx_info.tx_rate == ODM_RATE1M) {
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tx_info.signal_field = 0xa; /*rate = 1M*/
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tx_info.service_field = 0x0;
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if (dm->support_ic_type & ODM_RTL8723F) {
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tx_info.service_field_bit2= 0x1;
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tx_info.packet_length = 1000; /*1000 bytes*/
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}
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tx_info.length = 8000; /*d'8000 us=1000 bytes*/
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tx_info.crc16[0] = 0x60;
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tx_info.crc16[1] = 0x8e;
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/*long preamble*/
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tx_info.is_short_preamble = false;
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tx_info.sfd = 0xf3a0;
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} else if (tx_info.tx_rate == ODM_RATE6M) {
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/*l-sig[3:0] = rate = 6M = 0xb*/
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/*l-sig[16:5] = length = 1000 bytes*/
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/*l-sig[17] = parity = 1*/
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tx_info.lsig[0] = 0xb;
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tx_info.lsig[1] = 0x7d;
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tx_info.lsig[2] = 0x2;
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}
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phydm_print_rate_2_buff(dm, tx_info.tx_rate, dbg_buf,
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PHYDM_SNPRINT_SIZE);
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PDM_SNPF(out_len, used, output + used, out_len - used,
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"rate=%s, count=%d, pkt_interval=500(us), length=1000(bytes)\n",
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dbg_buf, tx_info.packet_count);
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if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
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PDM_SNPF(out_len, used, output + used, out_len - used,
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"check trx idle failed, please try again.\n");
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return;
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}
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phydm_reset_bb_hw_cnt(dm);
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phydm_set_pmac_tx_jgr3(dm, &tx_info, RF_PATH_A);
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PDM_SNPF(out_len, used, output + used, out_len - used,
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"pmac_tx enabled, please wait for tx_cnt = %d\n",
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tx_info.packet_count);
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while (1) {
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if (phydm_is_cck_rate(dm, tx_info.tx_rate))
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tx_cnt = odm_get_bb_reg(dm, R_0x2de4,
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MASKLWORD);
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else
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tx_cnt = odm_get_bb_reg(dm, R_0x2de0,
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MASKLWORD);
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if (tx_cnt >= tx_info.packet_count || poll_cnt >= 10)
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break;
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ODM_delay_ms(100);
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poll_cnt++;
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}
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if (tx_cnt < tx_info.packet_count)
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PDM_SNPF(out_len, used, output + used, out_len - used,
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"polling time out(1s), tx_cnt = %d\n", tx_cnt);
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else
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PDM_SNPF(out_len, used, output + used, out_len - used,
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"pmac_tx finished, poll_cnt = %d\n", poll_cnt);
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tx_info.en_pmac_tx = false;
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phydm_set_pmac_tx(dm, &tx_info, RF_PATH_A);
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phydm_set_tmac_tx(dm);
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PDM_SNPF(out_len, used, output + used, out_len - used,
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"Stop pmac_tx and turn on true mac mode.\n");
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phydm_stop_ic_trx(dm, PHYDM_REVERT);
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}
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*_used = used;
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*_out_len = out_len;
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}
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#endif
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