/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2016 Linaro Ltd.
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* Copyright 2016 ZTE Corporation.
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*/
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#ifndef __ZX_VOU_REGS_H__
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#define __ZX_VOU_REGS_H__
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/* Sub-module offset */
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#define MAIN_GL_OFFSET 0x130
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#define MAIN_GL_CSC_OFFSET 0x580
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#define MAIN_CHN_CSC_OFFSET 0x6c0
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#define MAIN_HBSC_OFFSET 0x820
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#define MAIN_DITHER_OFFSET 0x960
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#define MAIN_RSZ_OFFSET 0x600 /* OTFPPU sub-module */
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#define AUX_GL_OFFSET 0x200
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#define AUX_GL_CSC_OFFSET 0x5d0
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#define AUX_CHN_CSC_OFFSET 0x710
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#define AUX_HBSC_OFFSET 0x860
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#define AUX_DITHER_OFFSET 0x970
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#define AUX_RSZ_OFFSET 0x800
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#define OSD_VL0_OFFSET 0x040
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#define OSD_VL_OFFSET(i) (OSD_VL0_OFFSET + 0x050 * (i))
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#define HBSC_VL0_OFFSET 0x760
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#define HBSC_VL_OFFSET(i) (HBSC_VL0_OFFSET + 0x040 * (i))
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#define RSZ_VL1_U0 0xa00
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#define RSZ_VL_OFFSET(i) (RSZ_VL1_U0 + 0x200 * (i))
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/* OSD (GPC_GLOBAL) registers */
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#define OSD_INT_STA 0x04
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#define OSD_INT_CLRSTA 0x08
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#define OSD_INT_MSK 0x0c
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#define OSD_INT_AUX_UPT BIT(14)
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#define OSD_INT_MAIN_UPT BIT(13)
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#define OSD_INT_GL1_LBW BIT(10)
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#define OSD_INT_GL0_LBW BIT(9)
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#define OSD_INT_VL2_LBW BIT(8)
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#define OSD_INT_VL1_LBW BIT(7)
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#define OSD_INT_VL0_LBW BIT(6)
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#define OSD_INT_BUS_ERR BIT(3)
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#define OSD_INT_CFG_ERR BIT(2)
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#define OSD_INT_ERROR (\
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OSD_INT_GL1_LBW | OSD_INT_GL0_LBW | \
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OSD_INT_VL2_LBW | OSD_INT_VL1_LBW | OSD_INT_VL0_LBW | \
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OSD_INT_BUS_ERR | OSD_INT_CFG_ERR \
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)
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#define OSD_INT_ENABLE (OSD_INT_ERROR | OSD_INT_AUX_UPT | OSD_INT_MAIN_UPT)
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#define OSD_CTRL0 0x10
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#define OSD_CTRL0_VL0_EN BIT(13)
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#define OSD_CTRL0_VL0_SEL BIT(12)
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#define OSD_CTRL0_VL1_EN BIT(11)
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#define OSD_CTRL0_VL1_SEL BIT(10)
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#define OSD_CTRL0_VL2_EN BIT(9)
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#define OSD_CTRL0_VL2_SEL BIT(8)
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#define OSD_CTRL0_GL0_EN BIT(7)
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#define OSD_CTRL0_GL0_SEL BIT(6)
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#define OSD_CTRL0_GL1_EN BIT(5)
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#define OSD_CTRL0_GL1_SEL BIT(4)
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#define OSD_RST_CLR 0x1c
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#define RST_PER_FRAME BIT(19)
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/* Main/Aux channel registers */
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#define OSD_MAIN_CHN 0x470
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#define OSD_AUX_CHN 0x4d0
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#define CHN_CTRL0 0x00
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#define CHN_ENABLE BIT(0)
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#define CHN_CTRL1 0x04
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#define CHN_SCREEN_W_SHIFT 18
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#define CHN_SCREEN_W_MASK (0x1fff << CHN_SCREEN_W_SHIFT)
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#define CHN_SCREEN_H_SHIFT 5
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#define CHN_SCREEN_H_MASK (0x1fff << CHN_SCREEN_H_SHIFT)
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#define CHN_UPDATE 0x08
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#define CHN_INTERLACE_BUF_CTRL 0x24
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#define CHN_INTERLACE_EN BIT(2)
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/* Dither registers */
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#define OSD_DITHER_CTRL0 0x00
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#define DITHER_BYSPASS BIT(31)
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/* TIMING_CTRL registers */
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#define TIMING_TC_ENABLE 0x04
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#define AUX_TC_EN BIT(1)
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#define MAIN_TC_EN BIT(0)
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#define FIR_MAIN_ACTIVE 0x08
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#define FIR_AUX_ACTIVE 0x0c
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#define V_ACTIVE_SHIFT 16
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#define V_ACTIVE_MASK (0xffff << V_ACTIVE_SHIFT)
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#define H_ACTIVE_SHIFT 0
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#define H_ACTIVE_MASK (0xffff << H_ACTIVE_SHIFT)
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#define FIR_MAIN_H_TIMING 0x10
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#define FIR_MAIN_V_TIMING 0x14
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#define FIR_AUX_H_TIMING 0x18
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#define FIR_AUX_V_TIMING 0x1c
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#define SYNC_WIDE_SHIFT 22
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#define SYNC_WIDE_MASK (0x3ff << SYNC_WIDE_SHIFT)
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#define BACK_PORCH_SHIFT 11
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#define BACK_PORCH_MASK (0x7ff << BACK_PORCH_SHIFT)
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#define FRONT_PORCH_SHIFT 0
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#define FRONT_PORCH_MASK (0x7ff << FRONT_PORCH_SHIFT)
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#define TIMING_CTRL 0x20
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#define AUX_POL_SHIFT 3
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#define AUX_POL_MASK (0x7 << AUX_POL_SHIFT)
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#define MAIN_POL_SHIFT 0
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#define MAIN_POL_MASK (0x7 << MAIN_POL_SHIFT)
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#define POL_DE_SHIFT 2
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#define POL_VSYNC_SHIFT 1
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#define POL_HSYNC_SHIFT 0
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#define TIMING_INT_CTRL 0x24
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#define TIMING_INT_STATE 0x28
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#define TIMING_INT_AUX_FRAME BIT(3)
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#define TIMING_INT_MAIN_FRAME BIT(1)
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#define TIMING_INT_AUX_FRAME_SEL_VSW (0x2 << 10)
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#define TIMING_INT_MAIN_FRAME_SEL_VSW (0x2 << 6)
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#define TIMING_INT_ENABLE (\
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TIMING_INT_MAIN_FRAME_SEL_VSW | TIMING_INT_AUX_FRAME_SEL_VSW | \
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TIMING_INT_MAIN_FRAME | TIMING_INT_AUX_FRAME \
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)
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#define TIMING_MAIN_SHIFT 0x2c
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#define TIMING_AUX_SHIFT 0x30
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#define H_SHIFT_VAL 0x0048
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#define V_SHIFT_VAL 0x0001
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#define SCAN_CTRL 0x34
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#define AUX_PI_EN BIT(19)
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#define MAIN_PI_EN BIT(18)
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#define AUX_INTERLACE_SEL BIT(1)
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#define MAIN_INTERLACE_SEL BIT(0)
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#define SEC_V_ACTIVE 0x38
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#define SEC_VACT_MAIN_SHIFT 0
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#define SEC_VACT_MAIN_MASK (0xffff << SEC_VACT_MAIN_SHIFT)
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#define SEC_VACT_AUX_SHIFT 16
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#define SEC_VACT_AUX_MASK (0xffff << SEC_VACT_AUX_SHIFT)
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#define SEC_MAIN_V_TIMING 0x3c
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#define SEC_AUX_V_TIMING 0x40
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#define TIMING_MAIN_PI_SHIFT 0x68
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#define TIMING_AUX_PI_SHIFT 0x6c
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#define H_PI_SHIFT_VAL 0x000f
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#define V_ACTIVE(x) (((x) << V_ACTIVE_SHIFT) & V_ACTIVE_MASK)
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#define H_ACTIVE(x) (((x) << H_ACTIVE_SHIFT) & H_ACTIVE_MASK)
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#define SYNC_WIDE(x) (((x) << SYNC_WIDE_SHIFT) & SYNC_WIDE_MASK)
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#define BACK_PORCH(x) (((x) << BACK_PORCH_SHIFT) & BACK_PORCH_MASK)
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#define FRONT_PORCH(x) (((x) << FRONT_PORCH_SHIFT) & FRONT_PORCH_MASK)
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/* DTRC registers */
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#define DTRC_F0_CTRL 0x2c
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#define DTRC_F1_CTRL 0x5c
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#define DTRC_DECOMPRESS_BYPASS BIT(17)
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#define DTRC_DETILE_CTRL 0x68
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#define TILE2RASTESCAN_BYPASS_MODE BIT(30)
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#define DETILE_ARIDR_MODE_MASK (0x3 << 0)
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#define DETILE_ARID_ALL 0
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#define DETILE_ARID_IN_ARIDR 1
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#define DETILE_ARID_BYP_BUT_ARIDR 2
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#define DETILE_ARID_IN_ARIDR2 3
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#define DTRC_ARID 0x6c
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#define DTRC_ARID3_SHIFT 24
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#define DTRC_ARID3_MASK (0xff << DTRC_ARID3_SHIFT)
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#define DTRC_ARID2_SHIFT 16
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#define DTRC_ARID2_MASK (0xff << DTRC_ARID2_SHIFT)
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#define DTRC_ARID1_SHIFT 8
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#define DTRC_ARID1_MASK (0xff << DTRC_ARID1_SHIFT)
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#define DTRC_ARID0_SHIFT 0
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#define DTRC_ARID0_MASK (0xff << DTRC_ARID0_SHIFT)
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#define DTRC_DEC2DDR_ARID 0x70
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#define DTRC_ARID3(x) (((x) << DTRC_ARID3_SHIFT) & DTRC_ARID3_MASK)
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#define DTRC_ARID2(x) (((x) << DTRC_ARID2_SHIFT) & DTRC_ARID2_MASK)
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#define DTRC_ARID1(x) (((x) << DTRC_ARID1_SHIFT) & DTRC_ARID1_MASK)
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#define DTRC_ARID0(x) (((x) << DTRC_ARID0_SHIFT) & DTRC_ARID0_MASK)
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/* VOU_CTRL registers */
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#define VOU_INF_EN 0x00
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#define VOU_INF_CH_SEL 0x04
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#define VOU_INF_DATA_SEL 0x08
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#define VOU_SOFT_RST 0x14
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#define VOU_CLK_SEL 0x18
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#define VGA_AUX_DIV_SHIFT 29
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#define VGA_MAIN_DIV_SHIFT 26
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#define PIC_MAIN_DIV_SHIFT 23
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#define PIC_AUX_DIV_SHIFT 20
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#define VOU_CLK_VL2_SEL BIT(8)
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#define VOU_CLK_VL1_SEL BIT(7)
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#define VOU_CLK_VL0_SEL BIT(6)
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#define VOU_CLK_GL1_SEL BIT(5)
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#define VOU_CLK_GL0_SEL BIT(4)
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#define VOU_DIV_PARA 0x1c
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#define DIV_PARA_UPDATE BIT(31)
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#define TVENC_AUX_DIV_SHIFT 28
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#define HDMI_AUX_PNX_DIV_SHIFT 25
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#define HDMI_MAIN_PNX_DIV_SHIFT 22
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#define HDMI_AUX_DIV_SHIFT 19
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#define HDMI_MAIN_DIV_SHIFT 16
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#define TVENC_MAIN_DIV_SHIFT 13
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#define INF_AUX_DIV_SHIFT 9
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#define INF_MAIN_DIV_SHIFT 6
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#define LAYER_AUX_DIV_SHIFT 3
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#define LAYER_MAIN_DIV_SHIFT 0
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#define VOU_CLK_REQEN 0x20
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#define VOU_CLK_EN 0x24
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#define VOU_INF_HDMI_CTRL 0x30
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#define VOU_HDMI_AUD_MASK 0x1f
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/* OTFPPU_CTRL registers */
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#define OTFPPU_RSZ_DATA_SOURCE 0x04
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#endif /* __ZX_VOU_REGS_H__ */
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