// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Zorro Liu <zorro.liu@rock-chips.com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/pm_runtime.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "ebc_tcon.h"
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#define HIWORD_UPDATE(x, l, h) (((x) << (l)) | (GENMASK(h, l) << 16))
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#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
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/* eink register define */
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#define EINK_IP_ENABLE 0x00
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#define EINK_SFT_UPDATE 0x04
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#define EINK_SIT_UPDATE 0x08
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#define EINK_PRE_IMAGE_BUF_ADDR 0x0c
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#define EINK_CUR_IMAGE_BUF_ADDR 0x10
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#define EINK_IMAGE_PROCESS_BUF_ADDR 0x14
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#define EINK_LINE_DATA_ADDR_OFFSET 0x18
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#define EINK_IMAGE_WIDTH 0x1c
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#define EINK_IMAGE_HEIGHT 0x20
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#define EINK_DATA_FORMAT 0x24
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#define EINK_IP_STATUS 0x28
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#define EINK_IP_VERSION 0x2c
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#define EINK_IP_CLR_INT 0x30
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#define EINK_INT_SETTING0 0x34
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#define EINK_INT_SETTING1 0x38
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#define EINK_INT_SETTING2 0x3c
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#define EINK_INT_SETTING3 0x40
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#define EINK_INT_SETTING4 0x44
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#define EINK_INT_SETTING5 0x48
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#define EINK_INT_SETTING6 0x4c
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#define EINK_INT_SETTING7 0x50
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#define EINK_WF_SETTING0 0x54
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#define EINK_WF_SETTING1 0x58
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#define EINK_WF_SETTING2 0x5c
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#define EINK_WF_SETTING3 0x60
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#define EINK_WF_SETTING4 0x64
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#define EINK_WF_SETTING5 0x68
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#define EINK_WF_SETTING6 0x6c
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#define EINK_WF_SETTING7 0x70
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struct eink_reg_data {
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int addr;
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int value;
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};
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static const struct eink_reg_data PANEL_1200x825_INIT[] = {
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{ EINK_SFT_UPDATE, 0x00030001 },
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{ EINK_SIT_UPDATE, 0x00050000 },
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{ EINK_LINE_DATA_ADDR_OFFSET, 0x000004b0 }, //width
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{ EINK_IMAGE_WIDTH, 0x000004af }, //width - 1
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{ EINK_IMAGE_HEIGHT, 0x00000338 }, //height - 1
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{ EINK_INT_SETTING0, 0x0e56676f },
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{ EINK_INT_SETTING1, 0x40674408 },
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{ EINK_INT_SETTING2, 0xd7eb7743 },
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{ EINK_INT_SETTING3, 0x19414d35 },
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{ EINK_INT_SETTING4, 0x12561c00 },
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{ EINK_INT_SETTING5, 0x05552e0a },
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{ EINK_INT_SETTING6, 0x4a400e10 },
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{ EINK_INT_SETTING7, 0x15496e2b },
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{ EINK_WF_SETTING0, 0xb3f33a52 },
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{ EINK_WF_SETTING1, 0x2042b122 },
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{ EINK_WF_SETTING2, 0xbdb0f3be },
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{ EINK_WF_SETTING3, 0xe289a0ca },
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{ EINK_WF_SETTING4, 0xb0d3b2c8 },
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{ EINK_WF_SETTING5, 0x3a32ab20 },
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{ EINK_WF_SETTING6, 0xa69a634c },
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{ EINK_WF_SETTING7, 0xd87af2c0 },
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};
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static const struct eink_reg_data PANEL_1872x1404_INIT[] = {
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{ EINK_SFT_UPDATE, 0x00030001 },
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{ EINK_SIT_UPDATE, 0x00050000 },
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{ EINK_LINE_DATA_ADDR_OFFSET, 0x00000750 }, //width
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{ EINK_IMAGE_WIDTH, 0x0000074f }, //width - 1
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{ EINK_IMAGE_HEIGHT, 0x0000057c }, //height -1
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{ EINK_INT_SETTING0, 0x0e56676f },
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{ EINK_INT_SETTING1, 0x40674408 },
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{ EINK_INT_SETTING2, 0xb14a4643 },
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{ EINK_INT_SETTING3, 0x19414d35 },
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{ EINK_INT_SETTING4, 0x12561c00 },
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{ EINK_INT_SETTING5, 0x05552e0a },
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{ EINK_INT_SETTING6, 0x4a400e10 },
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{ EINK_INT_SETTING7, 0x15496e2b },
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{ EINK_WF_SETTING0, 0xb3f33a52 },
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{ EINK_WF_SETTING1, 0x2042b122 },
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{ EINK_WF_SETTING2, 0x34b0708b },
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{ EINK_WF_SETTING3, 0xe289a0ca },
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{ EINK_WF_SETTING4, 0xb0d3b2c8 },
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{ EINK_WF_SETTING5, 0x3a32ab20 },
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{ EINK_WF_SETTING6, 0x2f9ae079 },
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{ EINK_WF_SETTING7, 0xd87af2c0 },
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};
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static inline void tcon_write(struct eink_tcon *tcon, unsigned int reg,
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unsigned int value)
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{
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regmap_write(tcon->regmap_base, reg, value);
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}
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static inline unsigned int tcon_read(struct eink_tcon *tcon, unsigned int reg)
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{
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unsigned int value;
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regmap_read(tcon->regmap_base, reg, &value);
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return value;
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}
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static inline void tcon_update_bits(struct eink_tcon *tcon, unsigned int reg,
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unsigned int mask, unsigned int val)
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{
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regmap_update_bits(tcon->regmap_base, reg, mask, val);
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}
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static int tcon_enable(struct eink_tcon *tcon, struct ebc_panel *panel)
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{
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int reg_num = 0;
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int i;
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const struct eink_reg_data *pre_init_reg;
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clk_prepare_enable(tcon->pclk);
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clk_prepare_enable(tcon->hclk);
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pm_runtime_get_sync(tcon->dev);
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if ((panel->width == 1872) && (panel->height == 1404)) {
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pre_init_reg = PANEL_1872x1404_INIT;
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reg_num = ARRAY_SIZE(PANEL_1872x1404_INIT);
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} else if ((panel->width == 1200) && (panel->height == 825)) {
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pre_init_reg = PANEL_1200x825_INIT;
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reg_num = ARRAY_SIZE(PANEL_1200x825_INIT);
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} else {
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pre_init_reg = PANEL_1872x1404_INIT;
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reg_num = ARRAY_SIZE(PANEL_1872x1404_INIT);
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}
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for (i = 0; i < reg_num; i++) {
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tcon_write(tcon, pre_init_reg[i].addr, pre_init_reg[i].value);
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}
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enable_irq(tcon->irq);
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return 0;
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}
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static void tcon_disable(struct eink_tcon *tcon)
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{
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disable_irq(tcon->irq);
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pm_runtime_put_sync(tcon->dev);
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clk_disable_unprepare(tcon->hclk);
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clk_disable_unprepare(tcon->pclk);
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}
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static void tcon_image_addr_set(struct eink_tcon *tcon, u32 pre_image_buf_addr,
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u32 cur_image_buf_addr, u32 image_process_buf_addr)
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{
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tcon_write(tcon, EINK_PRE_IMAGE_BUF_ADDR, pre_image_buf_addr);
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tcon_write(tcon, EINK_CUR_IMAGE_BUF_ADDR, cur_image_buf_addr);
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tcon_write(tcon, EINK_IMAGE_PROCESS_BUF_ADDR, image_process_buf_addr);
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}
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static void tcon_frame_start(struct eink_tcon *tcon)
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{
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tcon_write(tcon, EINK_IP_ENABLE, 1);
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}
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static irqreturn_t tcon_irq_hanlder(int irq, void *dev_id)
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{
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struct eink_tcon *tcon = (struct eink_tcon *)dev_id;
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u32 intr_status;
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intr_status = tcon_read(tcon, EINK_IP_STATUS);
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if (intr_status & 0x1) {
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tcon_update_bits(tcon, EINK_IP_CLR_INT, 0x1, 0x1);
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if (tcon->dsp_end_callback)
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tcon->dsp_end_callback();
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}
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return IRQ_HANDLED;
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}
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static struct regmap_config eink_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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static int eink_tcon_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct eink_tcon *tcon;
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struct resource *res;
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int ret;
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tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
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if (!tcon)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tcon->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(tcon->regs))
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return PTR_ERR(tcon->regs);
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tcon->len = resource_size(res);
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eink_regmap_config.max_register = resource_size(res) - 4;
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eink_regmap_config.name = "rockchip,eink_tcon";
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tcon->regmap_base = devm_regmap_init_mmio(dev, tcon->regs, &eink_regmap_config);
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if (IS_ERR(tcon->regmap_base))
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return PTR_ERR(tcon->regmap_base);
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tcon->hclk = devm_clk_get(dev, "hclk");
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if (IS_ERR(tcon->hclk)) {
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ret = PTR_ERR(tcon->hclk);
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dev_err(dev, "failed to get hclk clock: %d\n", ret);
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return ret;
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}
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tcon->pclk = devm_clk_get(dev, "pclk");
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if (IS_ERR(tcon->pclk)) {
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ret = PTR_ERR(tcon->pclk);
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dev_err(dev, "failed to get dclk clock: %d\n", ret);
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return ret;
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}
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tcon->irq = platform_get_irq(pdev, 0);
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if (tcon->irq < 0) {
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dev_err(dev, "No IRQ resource!\n");
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return tcon->irq;
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}
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irq_set_status_flags(tcon->irq, IRQ_NOAUTOEN);
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ret = devm_request_irq(dev, tcon->irq, tcon_irq_hanlder,
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0, dev_name(dev), tcon);
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if (ret < 0) {
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dev_err(dev, "failed to requeset irq: %d\n", ret);
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return ret;
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}
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tcon->dev = dev;
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tcon->enable = tcon_enable;
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tcon->disable = tcon_disable;
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tcon->image_addr_set = tcon_image_addr_set;
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tcon->frame_start = tcon_frame_start;
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platform_set_drvdata(pdev, tcon);
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pm_runtime_enable(dev);
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return 0;
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}
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static int eink_tcon_remove(struct platform_device *pdev)
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{
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static const struct of_device_id eink_tcon_of_match[] = {
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{ .compatible = "rockchip,rk3568-eink-tcon" },
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{}
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};
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MODULE_DEVICE_TABLE(of, eink_tcon_of_match);
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static struct platform_driver eink_tcon_driver = {
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.driver = {
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.name = "rk-eink-tcon",
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.of_match_table = eink_tcon_of_match,
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},
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.probe = eink_tcon_probe,
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.remove = eink_tcon_remove,
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};
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module_platform_driver(eink_tcon_driver);
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MODULE_AUTHOR("Zorro Liu <zorro.liu@rock-chips.com>");
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MODULE_DESCRIPTION("ROCKCHIP EINK tcon driver");
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MODULE_LICENSE("GPL v2");
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