// SPDX-License-Identifier: GPL-2.0
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/*
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* Synopsys DesignWare Cores HDCP Controller
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*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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*
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* Author: Zhang Yubing <yubing.zhang@rock-chips.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/miscdevice.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/uaccess.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/mfd/syscon.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/rockchip/rockchip_sip.h>
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#include <uapi/misc/dw_hdcp2.h>
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#define VO0_GRF_VO0_STS0 0x20
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#define DP1_CONNECT_HDCP0_STATUS BIT(24)
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#define DP0_CONNECT_HDCP0_STATUS BIT(8)
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#define VO0_GRF_VO0_STS3 0x2C
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#define HDCP0_BOOT_STATUS BIT(8)
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#define VO1_GRF_VO1_STS3 0x3C
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#define HDMITX0_CONNECT_HDCP1_STATUS BIT(20)
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#define HDCP1_BOOT_STATUS BIT(16)
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#define VO1_GRF_VO1_STS4 0x40
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#define HDMITX1_CONNECT_HDCP1_STATUS BIT(0)
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#define HDMIRX_CONNECT_HDCP1_STATUS BIT(8)
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/**
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* struct hl_device - hdcp host library device structure
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* each hdcp controller attach to a hl_device, it include
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* code memory info, data memory info and hpi(apb) interface
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* info
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*/
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struct hl_device {
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bool allocated;
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bool initialized;
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bool code_loaded;
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bool code_is_phys_mem;
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dma_addr_t code_base;
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uint32_t code_size;
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uint8_t *code;
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bool data_is_phys_mem;
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dma_addr_t data_base;
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uint32_t data_size;
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uint8_t *data;
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/** @hpi_respurce: resource of HPI interface */
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struct resource *hpi_resource;
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/** @hpi: base address of HPI registers */
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uint8_t __iomem *hpi;
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};
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struct dw_hdcp {
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struct device *dev;
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struct miscdevice misc_dev;
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struct hl_device hl_dev;
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struct regmap *vo_grf;
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struct reset_control *rsts_bulk;
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struct clk_bulk_data *clks;
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int num_clks;
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int id;
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bool is_suspend;
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};
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enum {
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HDCP_PORT0 = 0,
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HDCP_PORT1,
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HDCP_PORT2,
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};
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static void dw_hdcp_free_hl_dev_slot(struct hl_device *hl_dev);
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static void dw_hdcp_free_hl(struct dw_hdcp *hdcp)
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{
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dw_hdcp_free_hl_dev_slot(&hdcp->hl_dev);
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hdcp->hl_dev.code_loaded = false;
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}
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static void dw_hdcp_reset(struct dw_hdcp *hdcp)
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{
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int ret;
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reset_control_assert(hdcp->rsts_bulk);
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udelay(20);
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reset_control_deassert(hdcp->rsts_bulk);
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ret = sip_hdcpkey_init(hdcp->id);
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if (ret)
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dev_err(hdcp->dev, "load hdcp key failed\n");
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}
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static int dw_hdcp_set_reset(struct dw_hdcp *hdcp, void __user *arg)
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{
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u32 reset;
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if (!arg)
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return -EFAULT;
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if (copy_from_user(&reset, arg, sizeof(reset)))
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return -EFAULT;
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if (reset) {
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dev_info(hdcp->dev, "hdcp reset\n");
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dw_hdcp_free_hl(hdcp);
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dw_hdcp_reset(hdcp);
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}
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return 0;
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}
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static int dw_hdcp_get_status(struct dw_hdcp *hdcp, void __user *arg)
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{
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struct hl_drv_ioc_status status;
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u32 val = 0;
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u32 connected_status = 0;
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u32 booted_status = 0;
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if (!arg)
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return -EFAULT;
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if (!hdcp->is_suspend) {
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if (hdcp->id) {
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regmap_read(hdcp->vo_grf, VO1_GRF_VO1_STS3, &val);
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if (val & HDMITX0_CONNECT_HDCP1_STATUS)
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connected_status |= 1 << HDCP_PORT1;
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if (val & HDCP1_BOOT_STATUS)
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booted_status = 1;
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regmap_read(hdcp->vo_grf, VO1_GRF_VO1_STS4, &val);
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if (val & HDMITX1_CONNECT_HDCP1_STATUS)
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connected_status |= 1 << HDCP_PORT2;
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if (val & HDMIRX_CONNECT_HDCP1_STATUS)
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connected_status |= 1 << HDCP_PORT0;
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} else {
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regmap_read(hdcp->vo_grf, VO0_GRF_VO0_STS0, &val);
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if (val & DP0_CONNECT_HDCP0_STATUS)
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connected_status |= 1 << HDCP_PORT0;
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if (val & DP1_CONNECT_HDCP0_STATUS)
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connected_status |= 1 << HDCP_PORT1;
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regmap_read(hdcp->vo_grf, VO0_GRF_VO0_STS3, &val);
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if (val & HDCP0_BOOT_STATUS)
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booted_status = 1;
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}
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}
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status.connected_status = connected_status;
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status.booted_status = booted_status;
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if (copy_to_user(arg, &status, sizeof(status)))
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return -EFAULT;
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return 0;
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}
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/* HL_DRV_IOC_MEMINFO implementation */
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static long dw_hdcp_get_meminfo(struct hl_device *hl_dev, void __user *arg)
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{
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struct hl_drv_ioc_meminfo info;
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if (!arg)
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return -EFAULT;
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info.hpi_base = hl_dev->hpi_resource->start;
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info.code_base = hl_dev->code_base;
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info.code_size = hl_dev->code_size;
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info.data_base = hl_dev->data_base;
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info.data_size = hl_dev->data_size;
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if (copy_to_user(arg, &info, sizeof(info)))
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return -EFAULT;
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return 0;
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}
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/* HL_DRV_IOC_LOAD_CODE implementation */
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static long dw_hdcp_load_code(struct hl_device *hl_dev, struct hl_drv_ioc_code __user *arg)
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{
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struct hl_drv_ioc_code head;
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if (!arg || !hl_dev->code)
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return -EFAULT;
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if (copy_from_user(&head, arg, sizeof(head)))
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return -EFAULT;
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if (head.len > hl_dev->code_size)
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return -ENOSPC;
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if (hl_dev->code_loaded)
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return -EBUSY;
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if (copy_from_user(hl_dev->code, &arg->data, head.len))
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return -EFAULT;
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hl_dev->code_loaded = true;
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return 0;
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}
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/* HL_DRV_IOC_WRITE_DATA implementation */
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static long dw_hdcp_write_data(struct hl_device *hl_dev, struct hl_drv_ioc_data __user *arg)
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{
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struct hl_drv_ioc_data head;
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if (!arg || !hl_dev->data)
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return -EFAULT;
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if (copy_from_user(&head, arg, sizeof(head)))
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return -EFAULT;
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if (hl_dev->data_size < head.len)
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return -ENOSPC;
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if (hl_dev->data_size - head.len < head.offset)
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return -ENOSPC;
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if (copy_from_user(hl_dev->data + head.offset, &arg->data, head.len))
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return -EFAULT;
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return 0;
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}
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/* HL_DRV_IOC_READ_DATA implementation */
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static long dw_hdcp_read_data(struct hl_device *hl_dev, struct hl_drv_ioc_data __user *arg)
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{
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struct hl_drv_ioc_data head;
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if (!arg || !hl_dev->data)
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return -EFAULT;
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if (copy_from_user(&head, arg, sizeof(head)))
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return -EFAULT;
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if (hl_dev->data_size < head.len)
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return -ENOSPC;
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if (hl_dev->data_size - head.len < head.offset)
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return -ENOSPC;
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if (copy_to_user(&arg->data, hl_dev->data + head.offset, head.len))
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return -EFAULT;
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return 0;
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}
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/* HL_DRV_IOC_MEMSET_DATA implementation */
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static long dw_hdcp_set_data(struct hl_device *hl_dev, void __user *arg)
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{
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union {
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struct hl_drv_ioc_data data;
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unsigned char buf[sizeof(struct hl_drv_ioc_data) + 1];
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} u;
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if (!arg || !hl_dev->data)
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return -EFAULT;
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if (copy_from_user(&u.data, arg, sizeof(u.buf)))
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return -EFAULT;
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if (hl_dev->data_size < u.data.len)
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return -ENOSPC;
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if (hl_dev->data_size - u.data.len < u.data.offset)
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return -ENOSPC;
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memset(hl_dev->data + u.data.offset, u.data.data[0], u.data.len);
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return 0;
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}
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/* HL_DRV_IOC_READ_HPI implementation */
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static long dw_hdcp_hpi_read(struct hl_device *hl_dev, void __user *arg)
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{
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struct hl_drv_ioc_hpi_reg reg;
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if (!arg)
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return -EFAULT;
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if (copy_from_user(®, arg, sizeof(reg)))
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return -EFAULT;
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if ((reg.offset & 3) || reg.offset >= resource_size(hl_dev->hpi_resource))
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return -EINVAL;
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reg.value = ioread32(hl_dev->hpi + reg.offset);
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if (copy_to_user(arg, ®, sizeof(reg)))
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return -EFAULT;
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return 0;
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}
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/* HL_DRV_IOC_WRITE_HPI implementation */
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static long dw_hdcp_hpi_write(struct hl_device *hl_dev, void __user *arg)
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{
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struct hl_drv_ioc_hpi_reg reg;
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if (!arg)
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return -EFAULT;
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if (copy_from_user(®, arg, sizeof(reg)))
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return -EFAULT;
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if ((reg.offset & 3) || reg.offset >= resource_size(hl_dev->hpi_resource))
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return -EINVAL;
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iowrite32(reg.value, hl_dev->hpi + reg.offset);
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#ifdef TROOT_GRIFFIN
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if ((reg.offset == 0x38) && ((reg.value & 0x000000ff) == 0x08))
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hl_dev->code_loaded = false;
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#endif
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return 0;
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}
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static int dw_hdcp_check_hl_dev_slot(const struct hl_drv_ioc_meminfo *info,
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struct hl_device *hl_dev)
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{
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if (info->hpi_base == hl_dev->hpi_resource->start)
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return 0;
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return -EBUSY;
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}
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static void dw_hdcp_free_dma_areas(struct hl_device *hl_dev)
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{
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struct dw_hdcp *hdcp = container_of(hl_dev, struct dw_hdcp, hl_dev);
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if (!hl_dev->code_is_phys_mem && hl_dev->code) {
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dma_free_coherent(hdcp->dev, hl_dev->code_size, hl_dev->code, hl_dev->code_base);
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hl_dev->code = NULL;
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}
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if (!hl_dev->data_is_phys_mem && hl_dev->data) {
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dma_free_coherent(hdcp->dev, hl_dev->data_size, hl_dev->data, hl_dev->data_base);
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hl_dev->data = NULL;
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}
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}
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static int dw_hdcp_alloc_dma_areas(struct hl_device *hl_dev, const struct hl_drv_ioc_meminfo *info)
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{
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struct dw_hdcp *hdcp = container_of(hl_dev, struct dw_hdcp, hl_dev);
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hl_dev->code_size = info->code_size;
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hl_dev->code_is_phys_mem = (info->code_base != HL_DRIVER_ALLOCATE_DYNAMIC_MEM);
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hl_dev->data_size = info->data_size;
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hl_dev->data_is_phys_mem = (info->data_base != HL_DRIVER_ALLOCATE_DYNAMIC_MEM);
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if ((hl_dev->code_is_phys_mem && !hl_dev->code) ||
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(hl_dev->data_is_phys_mem && !hl_dev->data)) {
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dev_err(hdcp->dev, "hdcp don't support phys mem\n");
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return -ENOMEM;
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}
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hl_dev->code = dma_alloc_coherent(hdcp->dev, hl_dev->code_size,
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&hl_dev->code_base, GFP_KERNEL);
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if (!hl_dev->code)
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return -ENOMEM;
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hl_dev->data = dma_alloc_coherent(hdcp->dev, hl_dev->data_size,
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&hl_dev->data_base, GFP_KERNEL);
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if (!hl_dev->data) {
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dw_hdcp_free_dma_areas(hl_dev);
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return -ENOMEM;
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}
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return 0;
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}
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/* HL_DRV_IOC_INIT implementation */
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static long dw_hdcp_init(struct hl_device *hl_dev, void __user *arg)
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{
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struct hl_drv_ioc_meminfo info;
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int rc;
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if (!arg)
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return -EFAULT;
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if (copy_from_user(&info, arg, sizeof(info)))
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return -EFAULT;
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rc = dw_hdcp_check_hl_dev_slot(&info, hl_dev);
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if (rc)
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return -EMFILE;
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if (!hl_dev->initialized) {
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rc = dw_hdcp_alloc_dma_areas(hl_dev, &info);
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if (rc < 0)
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goto err_free;
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hl_dev->initialized = true;
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}
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return 0;
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err_free:
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dw_hdcp_free_dma_areas(hl_dev);
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hl_dev->initialized = false;
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return rc;
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}
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static void dw_hdcp_free_hl_dev_slot(struct hl_device *hl_dev)
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{
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if (hl_dev->initialized)
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dw_hdcp_free_dma_areas(hl_dev);
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hl_dev->initialized = false;
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}
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static long dw_hdcp_hld_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
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{
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struct hl_device *hl_dev;
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struct dw_hdcp *hdcp;
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struct miscdevice *misc_dev;
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void __user *data;
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if (!f)
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return -EFAULT;
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misc_dev = f->private_data;
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hdcp = container_of(misc_dev, struct dw_hdcp, misc_dev);
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hl_dev = &hdcp->hl_dev;
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data = (void __user *)arg;
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switch (cmd) {
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case HL_DRV_IOC_INIT:
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return dw_hdcp_init(hl_dev, data);
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case HL_DRV_IOC_MEMINFO:
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return dw_hdcp_get_meminfo(hl_dev, data);
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case HL_DRV_IOC_READ_HPI:
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return dw_hdcp_hpi_read(hl_dev, data);
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case HL_DRV_IOC_WRITE_HPI:
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return dw_hdcp_hpi_write(hl_dev, data);
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case HL_DRV_IOC_LOAD_CODE:
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return dw_hdcp_load_code(hl_dev, data);
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case HL_DRV_IOC_WRITE_DATA:
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return dw_hdcp_write_data(hl_dev, data);
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case HL_DRV_IOC_READ_DATA:
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return dw_hdcp_read_data(hl_dev, data);
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case HL_DRV_IOC_MEMSET_DATA:
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return dw_hdcp_set_data(hl_dev, data);
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case RK_DRV_IOC_GET_STATUS:
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return dw_hdcp_get_status(hdcp, data);
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case RK_DRV_IOC_RESET:
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return dw_hdcp_set_reset(hdcp, data);
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default:
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return -EINVAL;
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}
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return -ENOTTY;
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}
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static int dw_hdcp_hld_open(struct inode *inode, struct file *f)
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{
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struct dw_hdcp *hdcp;
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struct miscdevice *misc_dev;
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misc_dev = f->private_data;
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hdcp = container_of(misc_dev, struct dw_hdcp, misc_dev);
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pm_runtime_get_sync(hdcp->dev);
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return 0;
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}
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static int dw_hdcp_hld_release(struct inode *inode, struct file *f)
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{
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struct dw_hdcp *hdcp;
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struct miscdevice *misc_dev;
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misc_dev = f->private_data;
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hdcp = container_of(misc_dev, struct dw_hdcp, misc_dev);
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pm_runtime_put(hdcp->dev);
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return 0;
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}
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static const struct file_operations dw_hdcp_hld_file_operations = {
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#ifdef CONFIG_COMPAT
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.compat_ioctl = dw_hdcp_hld_ioctl,
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#else
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.unlocked_ioctl = dw_hdcp_hld_ioctl,
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#endif
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.open = dw_hdcp_hld_open,
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.release = dw_hdcp_hld_release,
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.owner = THIS_MODULE,
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};
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static int dw_hdcp_hld_init(struct dw_hdcp *hdcp, struct resource *res, void __iomem *base)
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{
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hdcp->hl_dev.allocated = false;
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hdcp->hl_dev.initialized = false;
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hdcp->hl_dev.code_loaded = false;
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hdcp->hl_dev.code = NULL;
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hdcp->hl_dev.data = NULL;
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hdcp->hl_dev.hpi_resource = res;
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hdcp->hl_dev.hpi = base;
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hdcp->misc_dev.name = devm_kasprintf(hdcp->dev, GFP_KERNEL, "hl_dev%d", hdcp->id);
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if (!hdcp->misc_dev.name)
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return -ENOMEM;
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hdcp->misc_dev.minor = MISC_DYNAMIC_MINOR;
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hdcp->misc_dev.fops = &dw_hdcp_hld_file_operations;
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return misc_register(&hdcp->misc_dev);
|
}
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static void dw_hdcp_hld_exit(struct dw_hdcp *hdcp)
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{
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dw_hdcp_free_hl_dev_slot(&hdcp->hl_dev);
|
|
misc_deregister(&hdcp->misc_dev);
|
}
|
|
static int dw_hdcp_probe(struct platform_device *pdev)
|
{
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struct device *dev = &pdev->dev;
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struct dw_hdcp *hdcp;
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struct resource *res;
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void __iomem *base;
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int id, ret;
|
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hdcp = devm_kzalloc(dev, sizeof(*hdcp), GFP_KERNEL);
|
if (!hdcp)
|
return -ENOMEM;
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
|
if (IS_ERR(base))
|
return PTR_ERR(base);
|
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id = of_alias_get_id(dev->of_node, "hdcp");
|
if (id < 0)
|
id = 0;
|
|
hdcp->id = id;
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hdcp->dev = dev;
|
|
hdcp->vo_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo-grf");
|
if (IS_ERR(hdcp->vo_grf)) {
|
dev_err(hdcp->dev, "Get vo-grf failed\n");
|
return -ENODEV;
|
}
|
|
hdcp->rsts_bulk = devm_reset_control_array_get_exclusive(dev);
|
if (IS_ERR(hdcp->rsts_bulk)) {
|
dev_err(dev, "Get resets failed\n");
|
return -ENODEV;
|
}
|
|
hdcp->num_clks = devm_clk_bulk_get_all(dev, &hdcp->clks);
|
if (hdcp->num_clks < 1) {
|
dev_err(dev, "Get clks failed\n");
|
return -ENODEV;
|
}
|
|
ret = dw_hdcp_hld_init(hdcp, res, base);
|
if (ret) {
|
dev_err(dev, "hld init failed\n");
|
return -ENODEV;
|
}
|
|
platform_set_drvdata(pdev, hdcp);
|
|
pm_runtime_enable(hdcp->dev);
|
|
return 0;
|
}
|
|
static int dw_hdcp_remove(struct platform_device *pdev)
|
{
|
struct dw_hdcp *hdcp = platform_get_drvdata(pdev);
|
|
dw_hdcp_hld_exit(hdcp);
|
|
pm_runtime_disable(hdcp->dev);
|
|
return 0;
|
}
|
|
static int dw_hdcp_runtime_suspend(struct device *dev)
|
{
|
struct dw_hdcp *hdcp = dev_get_drvdata(dev);
|
|
hdcp->is_suspend = true;
|
clk_bulk_disable_unprepare(hdcp->num_clks, hdcp->clks);
|
|
dw_hdcp_free_hl(hdcp);
|
|
return 0;
|
}
|
|
static int dw_hdcp_runtime_resume(struct device *dev)
|
{
|
struct dw_hdcp *hdcp = dev_get_drvdata(dev);
|
int ret;
|
|
ret = clk_bulk_prepare_enable(hdcp->num_clks, hdcp->clks);
|
if (ret)
|
dev_err(dev, "prepare enable clk bulk failed\n");
|
|
dw_hdcp_reset(hdcp);
|
|
hdcp->is_suspend = false;
|
return 0;
|
}
|
|
static const struct dev_pm_ops dw_hdcp_pm_ops = {
|
SET_RUNTIME_PM_OPS(dw_hdcp_runtime_suspend, dw_hdcp_runtime_resume, NULL)
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
|
};
|
|
static const struct of_device_id dw_hdcp_of_match[] = {
|
{.compatible = "rockchip,rk3588-hdcp",},
|
{}
|
};
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|
MODULE_DEVICE_TABLE(of, dw_hdcp_of_match);
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|
static struct platform_driver dw_hdcp_driver = {
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.probe = dw_hdcp_probe,
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.remove = dw_hdcp_remove,
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.driver = {
|
.name = "dw-hdcp",
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.of_match_table = dw_hdcp_of_match,
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.pm = &dw_hdcp_pm_ops,
|
},
|
};
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|
module_platform_driver(dw_hdcp_driver);
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|
MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>");
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Rockchip HDCP Host Library Driver");
|
