// SPDX-License-Identifier: GPL-2.0-only
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/*
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* DesignWare MIPI DSI Host Controller v1.02 driver
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*
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* Copyright (c) 2016 Linaro Limited.
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* Copyright (c) 2014-2016 Hisilicon Limited.
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*
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* Author:
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* Xinliang Liu <z.liuxinliang@hisilicon.com>
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* Xinliang Liu <xinliang.liu@linaro.org>
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* Xinwei Kong <kong.kongxinwei@hisilicon.com>
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* Da Lv <lvda3@hisilicon.com>
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_device.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_of.h>
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#include <drm/drm_print.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_simple_kms_helper.h>
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#include "../kirin_drm_dsi.h"
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#include "../dw_dsi_reg.h"
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#define MAX_TX_ESC_CLK 10
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static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
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{
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u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
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u32 tmp_kHz = req_kHz;
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u32 i = 0;
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u32 q_pll = 1;
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u32 m_pll = 0;
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u32 n_pll = 0;
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u32 r_pll = 1;
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u32 m_n = 0;
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u32 m_n_int = 0;
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u32 f_kHz = 0;
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u64 temp;
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/*
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* Find a rate >= req_kHz.
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*/
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do {
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f_kHz = tmp_kHz;
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for (i = 0; i < ARRAY_SIZE(dphy_range_info); i++)
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if (f_kHz >= dphy_range_info[i].min_range_kHz &&
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f_kHz <= dphy_range_info[i].max_range_kHz)
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break;
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if (i == ARRAY_SIZE(dphy_range_info)) {
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DRM_ERROR("%dkHz out of range\n", f_kHz);
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return 0;
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}
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phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M;
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phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel;
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if (phy->hstx_ckg_sel <= 7 &&
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phy->hstx_ckg_sel >= 4)
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q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);
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temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps;
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m_n_int = temp / (u64)1000000000;
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m_n = (temp % (u64)1000000000) / (u64)100000000;
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if (m_n_int % 2 == 0) {
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if (m_n * 6 >= 50) {
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n_pll = 2;
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m_pll = (m_n_int + 1) * n_pll;
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} else if (m_n * 6 >= 30) {
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n_pll = 3;
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m_pll = m_n_int * n_pll + 2;
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} else {
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n_pll = 1;
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m_pll = m_n_int * n_pll;
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}
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} else {
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if (m_n * 6 >= 50) {
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n_pll = 1;
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m_pll = (m_n_int + 1) * n_pll;
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} else if (m_n * 6 >= 30) {
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n_pll = 1;
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m_pll = (m_n_int + 1) * n_pll;
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} else if (m_n * 6 >= 10) {
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n_pll = 3;
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m_pll = m_n_int * n_pll + 1;
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} else {
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n_pll = 2;
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m_pll = m_n_int * n_pll;
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}
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}
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if (n_pll == 1) {
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phy->pll_fbd_p = 0;
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phy->pll_pre_div1p = 1;
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} else {
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phy->pll_fbd_p = n_pll;
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phy->pll_pre_div1p = 0;
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}
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if (phy->pll_fbd_2p <= 7 && phy->pll_fbd_2p >= 4)
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r_pll = 0x10 >> (7 - phy->pll_fbd_2p);
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if (m_pll == 2) {
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phy->pll_pre_p = 0;
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phy->pll_fbd_s = 0;
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phy->pll_fbd_div1f = 0;
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phy->pll_fbd_div5f = 1;
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} else if (m_pll >= 2 * 2 * r_pll && m_pll <= 2 * 4 * r_pll) {
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phy->pll_pre_p = m_pll / (2 * r_pll);
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phy->pll_fbd_s = 0;
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phy->pll_fbd_div1f = 1;
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phy->pll_fbd_div5f = 0;
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} else if (m_pll >= 2 * 5 * r_pll && m_pll <= 2 * 150 * r_pll) {
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if (((m_pll / (2 * r_pll)) % 2) == 0) {
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phy->pll_pre_p =
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(m_pll / (2 * r_pll)) / 2 - 1;
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phy->pll_fbd_s =
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(m_pll / (2 * r_pll)) % 2 + 2;
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} else {
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phy->pll_pre_p =
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(m_pll / (2 * r_pll)) / 2;
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phy->pll_fbd_s =
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(m_pll / (2 * r_pll)) % 2;
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}
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phy->pll_fbd_div1f = 0;
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phy->pll_fbd_div5f = 0;
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} else {
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phy->pll_pre_p = 0;
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phy->pll_fbd_s = 0;
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phy->pll_fbd_div1f = 0;
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phy->pll_fbd_div5f = 1;
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}
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f_kHz = (u64)1000000000 * (u64)m_pll /
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((u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
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if (f_kHz >= req_kHz)
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break;
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tmp_kHz += 10;
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} while (true);
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return f_kHz;
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}
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static void dsi_get_phy_params(u32 phy_req_kHz,
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struct mipi_phy_params *phy)
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{
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u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
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u32 phy_rate_kHz;
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u32 ui;
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memset(phy, 0, sizeof(*phy));
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phy_rate_kHz = dsi_calc_phy_rate(phy_req_kHz, phy);
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if (!phy_rate_kHz)
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return;
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ui = 1000000 / phy_rate_kHz;
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phy->clk_t_lpx = ROUND(50, 8 * ui);
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phy->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1;
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phy->clk_t_hs_zero = ROUND(262, 8 * ui);
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phy->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1);
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phy->clk_t_wakeup = ROUND(1000000, (ref_clk_ps / 1000) - 1);
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if (phy->clk_t_wakeup > 0xff)
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phy->clk_t_wakeup = 0xff;
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phy->data_t_wakeup = phy->clk_t_wakeup;
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phy->data_t_lpx = phy->clk_t_lpx;
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phy->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1;
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phy->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui);
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phy->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1);
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phy->data_t_ta_go = 3;
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phy->data_t_ta_get = 4;
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phy->pll_enbwt = 1;
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phy->clklp2hs_time = ROUND(407, 8 * ui) + 12;
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phy->clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui);
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phy->lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1;
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phy->hs2lp_time = phy->clkhs2lp_time;
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phy->clk_to_data_delay = 1 + phy->clklp2hs_time;
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phy->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) +
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phy->clkhs2lp_time;
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phy->lane_byte_clk_kHz = phy_rate_kHz / 8;
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phy->clk_division =
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DIV_ROUND_UP(phy->lane_byte_clk_kHz, MAX_TX_ESC_CLK);
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}
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static u32 dsi_get_dpi_color_coding(enum mipi_dsi_pixel_format format)
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{
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u32 val;
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/*
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* TODO: only support RGB888 now, to support more
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*/
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switch (format) {
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case MIPI_DSI_FMT_RGB888:
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val = DSI_24BITS_1;
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break;
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default:
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val = DSI_24BITS_1;
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break;
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}
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return val;
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}
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/*
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* dsi phy reg write function
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*/
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static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val)
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{
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u32 reg_write = 0x10000 + reg;
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/*
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* latch reg first
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*/
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writel(reg_write, base + PHY_TST_CTRL1);
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writel(0x02, base + PHY_TST_CTRL0);
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writel(0x00, base + PHY_TST_CTRL0);
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/*
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* then latch value
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*/
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writel(val, base + PHY_TST_CTRL1);
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writel(0x02, base + PHY_TST_CTRL0);
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writel(0x00, base + PHY_TST_CTRL0);
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}
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static void dsi_set_phy_timer(void __iomem *base,
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struct mipi_phy_params *phy,
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u32 lanes)
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{
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u32 val;
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/*
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* Set lane value and phy stop wait time.
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*/
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val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8);
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writel(val, base + PHY_IF_CFG);
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/*
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* Set phy clk division.
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*/
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val = readl(base + CLKMGR_CFG) | phy->clk_division;
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writel(val, base + CLKMGR_CFG);
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/*
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* Set lp and hs switching params.
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*/
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dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time);
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dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time);
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dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10),
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phy->clkhs2lp_time);
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dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10),
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phy->clklp2hs_time);
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dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8),
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phy->data_to_clk_delay);
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dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8),
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phy->clk_to_data_delay);
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}
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static void dsi_set_mipi_phy(void __iomem *base,
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struct mipi_phy_params *phy,
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u32 lanes)
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{
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u32 delay_count;
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u32 val;
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u32 i;
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/* phy timer setting */
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dsi_set_phy_timer(base, phy, lanes);
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/*
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* Reset to clean up phy tst params.
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*/
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writel(0, base + PHY_RSTZ);
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writel(0, base + PHY_TST_CTRL0);
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writel(1, base + PHY_TST_CTRL0);
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writel(0, base + PHY_TST_CTRL0);
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/*
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* Clock lane timing control setting: TLPX, THS-PREPARE,
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* THS-ZERO, THS-TRAIL, TWAKEUP.
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*/
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dsi_phy_tst_set(base, CLK_TLPX, phy->clk_t_lpx);
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dsi_phy_tst_set(base, CLK_THS_PREPARE, phy->clk_t_hs_prepare);
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dsi_phy_tst_set(base, CLK_THS_ZERO, phy->clk_t_hs_zero);
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dsi_phy_tst_set(base, CLK_THS_TRAIL, phy->clk_t_hs_trial);
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dsi_phy_tst_set(base, CLK_TWAKEUP, phy->clk_t_wakeup);
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/*
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* Data lane timing control setting: TLPX, THS-PREPARE,
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* THS-ZERO, THS-TRAIL, TTA-GO, TTA-GET, TWAKEUP.
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*/
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for (i = 0; i < lanes; i++) {
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dsi_phy_tst_set(base, DATA_TLPX(i), phy->data_t_lpx);
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dsi_phy_tst_set(base, DATA_THS_PREPARE(i),
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phy->data_t_hs_prepare);
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dsi_phy_tst_set(base, DATA_THS_ZERO(i), phy->data_t_hs_zero);
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dsi_phy_tst_set(base, DATA_THS_TRAIL(i), phy->data_t_hs_trial);
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dsi_phy_tst_set(base, DATA_TTA_GO(i), phy->data_t_ta_go);
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dsi_phy_tst_set(base, DATA_TTA_GET(i), phy->data_t_ta_get);
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dsi_phy_tst_set(base, DATA_TWAKEUP(i), phy->data_t_wakeup);
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}
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/*
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* physical configuration: I, pll I, pll II, pll III,
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* pll IV, pll V.
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*/
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dsi_phy_tst_set(base, PHY_CFG_I, phy->hstx_ckg_sel);
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val = (phy->pll_fbd_div5f << 5) + (phy->pll_fbd_div1f << 4) +
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(phy->pll_fbd_2p << 1) + phy->pll_enbwt;
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dsi_phy_tst_set(base, PHY_CFG_PLL_I, val);
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dsi_phy_tst_set(base, PHY_CFG_PLL_II, phy->pll_fbd_p);
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dsi_phy_tst_set(base, PHY_CFG_PLL_III, phy->pll_fbd_s);
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val = (phy->pll_pre_div1p << 7) + phy->pll_pre_p;
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dsi_phy_tst_set(base, PHY_CFG_PLL_IV, val);
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val = (5 << 5) + (phy->pll_vco_750M << 4) + (phy->pll_lpf_rs << 2) +
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phy->pll_lpf_cs;
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dsi_phy_tst_set(base, PHY_CFG_PLL_V, val);
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writel(PHY_ENABLECLK, base + PHY_RSTZ);
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udelay(1);
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writel(PHY_ENABLECLK | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
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udelay(1);
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writel(PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
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usleep_range(1000, 1500);
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/*
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* wait for phy's clock ready
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*/
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delay_count = 100;
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while (delay_count) {
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val = readl(base + PHY_STATUS);
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if ((BIT(0) | BIT(2)) & val)
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break;
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udelay(1);
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delay_count--;
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}
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if (!delay_count)
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DRM_INFO("phylock and phystopstateclklane is not ready.\n");
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}
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static void dsi_set_mode_timing(void __iomem *base,
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u32 lane_byte_clk_kHz,
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struct drm_display_mode *mode,
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enum mipi_dsi_pixel_format format)
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{
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u32 hfp, hbp, hsw, vfp, vbp, vsw;
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u32 hline_time;
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u32 hsa_time;
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u32 hbp_time;
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u32 pixel_clk_kHz;
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int htot, vtot;
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u32 val;
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u64 tmp;
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val = dsi_get_dpi_color_coding(format);
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writel(val, base + DPI_COLOR_CODING);
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val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 1 : 0) << 2;
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val |= (mode->flags & DRM_MODE_FLAG_NVSYNC ? 1 : 0) << 1;
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writel(val, base + DPI_CFG_POL);
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/*
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* The DSI IP accepts vertical timing using lines as normal,
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* but horizontal timing is a mixture of pixel-clocks for the
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* active region and byte-lane clocks for the blanking-related
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* timings. hfp is specified as the total hline_time in byte-
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* lane clocks minus hsa, hbp and active.
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*/
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pixel_clk_kHz = mode->clock;
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htot = mode->htotal;
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vtot = mode->vtotal;
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hfp = mode->hsync_start - mode->hdisplay;
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hbp = mode->htotal - mode->hsync_end;
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hsw = mode->hsync_end - mode->hsync_start;
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vfp = mode->vsync_start - mode->vdisplay;
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vbp = mode->vtotal - mode->vsync_end;
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vsw = mode->vsync_end - mode->vsync_start;
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if (vsw > 15) {
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DRM_DEBUG_DRIVER("vsw exceeded 15\n");
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vsw = 15;
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}
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hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz;
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hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz;
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tmp = (u64)htot * (u64)lane_byte_clk_kHz;
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hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz);
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/* all specified in byte-lane clocks */
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writel(hsa_time, base + VID_HSA_TIME);
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writel(hbp_time, base + VID_HBP_TIME);
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writel(hline_time, base + VID_HLINE_TIME);
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writel(vsw, base + VID_VSA_LINES);
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writel(vbp, base + VID_VBP_LINES);
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writel(vfp, base + VID_VFP_LINES);
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writel(mode->vdisplay, base + VID_VACTIVE_LINES);
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writel(mode->hdisplay, base + VID_PKT_SIZE);
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DRM_DEBUG_DRIVER("htot=%d, hfp=%d, hbp=%d, hsw=%d\n",
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htot, hfp, hbp, hsw);
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DRM_DEBUG_DRIVER("vtol=%d, vfp=%d, vbp=%d, vsw=%d\n",
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vtot, vfp, vbp, vsw);
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DRM_DEBUG_DRIVER("hsa_time=%d, hbp_time=%d, hline_time=%d\n",
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hsa_time, hbp_time, hline_time);
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}
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static void dsi_set_video_mode(void __iomem *base, unsigned long flags)
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{
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u32 val;
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u32 mode_mask = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
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MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
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u32 non_burst_sync_pulse = MIPI_DSI_MODE_VIDEO |
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MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
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u32 non_burst_sync_event = MIPI_DSI_MODE_VIDEO;
|
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/*
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* choose video mode type
|
*/
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if ((flags & mode_mask) == non_burst_sync_pulse)
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val = DSI_NON_BURST_SYNC_PULSES;
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else if ((flags & mode_mask) == non_burst_sync_event)
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val = DSI_NON_BURST_SYNC_EVENTS;
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else
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val = DSI_BURST_SYNC_PULSES_1;
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writel(val, base + VID_MODE_CFG);
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writel(PHY_TXREQUESTCLKHS, base + LPCLK_CTRL);
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writel(DSI_VIDEO_MODE, base + MODE_CFG);
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}
|
|
static void dsi_mipi_init(struct dw_dsi *dsi)
|
{
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struct dsi_hw_ctx *ctx = dsi->ctx;
|
struct mipi_phy_params *phy = &dsi->phy;
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struct drm_display_mode *mode = &dsi->cur_mode;
|
u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
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void __iomem *base = ctx->base;
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u32 dphy_req_kHz;
|
|
/*
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* count phy params
|
*/
|
dphy_req_kHz = mode->clock * bpp / dsi->lanes;
|
dsi_get_phy_params(dphy_req_kHz, phy);
|
|
/* reset Core */
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writel(RESET, base + PWR_UP);
|
|
/* set dsi phy params */
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dsi_set_mipi_phy(base, phy, dsi->lanes);
|
|
/* set dsi mode timing */
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dsi_set_mode_timing(base, phy->lane_byte_clk_kHz, mode, dsi->format);
|
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/* set dsi video mode */
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dsi_set_video_mode(base, dsi->mode_flags);
|
|
/* dsi wake up */
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writel(POWERUP, base + PWR_UP);
|
|
DRM_DEBUG_DRIVER("lanes=%d, pixel_clk=%d kHz, bytes_freq=%d kHz\n",
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dsi->lanes, mode->clock, phy->lane_byte_clk_kHz);
|
}
|
|
static void dsi_encoder_enable_sub(struct drm_encoder *encoder)
|
{
|
struct dw_dsi *dsi = encoder_to_dsi(encoder);
|
struct dsi_hw_ctx *ctx = dsi->ctx;
|
int ret;
|
|
if (dsi->enable)
|
return;
|
|
ret = clk_prepare_enable(ctx->pclk);
|
if (ret) {
|
DRM_ERROR("fail to enable pclk: %d\n", ret);
|
return;
|
}
|
|
dsi_mipi_init(dsi);
|
}
|
|
static enum drm_mode_status dsi_encoder_phy_mode_valid(
|
struct drm_encoder *encoder,
|
const struct drm_display_mode *mode)
|
{
|
struct dw_dsi *dsi = encoder_to_dsi(encoder);
|
struct mipi_phy_params phy;
|
u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
|
u32 req_kHz, act_kHz, lane_byte_clk_kHz;
|
|
/* Calculate the lane byte clk using the adjusted mode clk */
|
memset(&phy, 0, sizeof(phy));
|
req_kHz = mode->clock * bpp / dsi->lanes;
|
act_kHz = dsi_calc_phy_rate(req_kHz, &phy);
|
lane_byte_clk_kHz = act_kHz / 8;
|
|
DRM_DEBUG_DRIVER("Checking mode %ix%i-%i@%i clock: %i...",
|
mode->hdisplay, mode->vdisplay, bpp,
|
drm_mode_vrefresh(mode), mode->clock);
|
|
/*
|
* Make sure the adjusted mode clock and the lane byte clk
|
* have a common denominator base frequency
|
*/
|
if (mode->clock/dsi->lanes == lane_byte_clk_kHz/3) {
|
DRM_DEBUG_DRIVER("OK!\n");
|
return MODE_OK;
|
}
|
|
DRM_DEBUG_DRIVER("BAD!\n");
|
return MODE_BAD;
|
}
|
|
static enum drm_mode_status dsi_encoder_mode_valid(struct drm_encoder *encoder,
|
const struct drm_display_mode *mode)
|
|
{
|
const struct drm_crtc_helper_funcs *crtc_funcs = NULL;
|
struct drm_crtc *crtc = NULL;
|
struct drm_display_mode adj_mode;
|
enum drm_mode_status ret;
|
|
/*
|
* The crtc might adjust the mode, so go through the
|
* possible crtcs (technically just one) and call
|
* mode_fixup to figure out the adjusted mode before we
|
* validate it.
|
*/
|
drm_for_each_crtc(crtc, encoder->dev) {
|
/*
|
* reset adj_mode to the mode value each time,
|
* so we don't adjust the mode twice
|
*/
|
drm_mode_copy(&adj_mode, mode);
|
|
crtc_funcs = crtc->helper_private;
|
if (crtc_funcs && crtc_funcs->mode_fixup)
|
if (!crtc_funcs->mode_fixup(crtc, mode, &adj_mode))
|
return MODE_BAD;
|
|
ret = dsi_encoder_phy_mode_valid(encoder, &adj_mode);
|
if (ret != MODE_OK)
|
return ret;
|
}
|
return MODE_OK;
|
}
|
|
static int dsi_host_attach(struct mipi_dsi_host *host,
|
struct mipi_dsi_device *mdsi)
|
{
|
struct dw_dsi *dsi = host_to_dsi(host);
|
|
if (mdsi->lanes < 1 || mdsi->lanes > 4) {
|
DRM_ERROR("dsi device params invalid\n");
|
return -EINVAL;
|
}
|
|
dsi->lanes = mdsi->lanes;
|
dsi->format = mdsi->format;
|
dsi->mode_flags = mdsi->mode_flags;
|
|
return 0;
|
}
|
|
static int dsi_host_detach(struct mipi_dsi_host *host,
|
struct mipi_dsi_device *mdsi)
|
{
|
/* do nothing */
|
return 0;
|
}
|
|
static const struct mipi_dsi_host_ops dsi_host_ops = {
|
.attach = dsi_host_attach,
|
.detach = dsi_host_detach,
|
};
|
|
static int dsi_host_init(struct device *dev, struct dw_dsi *dsi)
|
{
|
struct mipi_dsi_host *host = &dsi->host;
|
int ret;
|
|
host->dev = dev;
|
host->ops = &dsi_host_ops;
|
ret = mipi_dsi_host_register(host);
|
if (ret) {
|
DRM_ERROR("failed to register dsi host\n");
|
return ret;
|
}
|
|
return 0;
|
}
|
|
static int dsi_parse_dt(struct platform_device *pdev, struct dw_dsi *dsi)
|
{
|
struct dsi_hw_ctx *ctx = dsi->ctx;
|
struct device_node *np = pdev->dev.of_node;
|
struct resource *res;
|
int ret;
|
|
/*
|
* Get the endpoint node. In our case, dsi has one output port1
|
* to which the external HDMI bridge is connected.
|
*/
|
ret = drm_of_find_panel_or_bridge(np, 1, 0, NULL, &dsi->bridge);
|
if (ret)
|
return ret;
|
|
ctx->pclk = devm_clk_get(&pdev->dev, "pclk");
|
if (IS_ERR(ctx->pclk)) {
|
DRM_ERROR("failed to get pclk clock\n");
|
return PTR_ERR(ctx->pclk);
|
}
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
ctx->base = devm_ioremap_resource(&pdev->dev, res);
|
if (IS_ERR(ctx->base)) {
|
DRM_ERROR("failed to remap dsi io region\n");
|
return PTR_ERR(ctx->base);
|
}
|
|
return 0;
|
}
|
|
const struct kirin_dsi_ops kirin_dsi_620 = {
|
.version = KIRIN620_DSI,
|
.parse_dt = dsi_parse_dt,
|
.host_init = dsi_host_init,
|
.encoder_enable = dsi_encoder_enable_sub,
|
.encoder_valid = dsi_encoder_mode_valid
|
};
|
|
MODULE_AUTHOR("Xinliang Liu <xinliang.liu@linaro.org>");
|
MODULE_AUTHOR("Xinliang Liu <z.liuxinliang@hisilicon.com>");
|
MODULE_AUTHOR("Xinwei Kong <kong.kongxinwei@hisilicon.com>");
|
MODULE_DESCRIPTION("DesignWare MIPI DSI Host Controller v1.02 driver");
|
MODULE_LICENSE("GPL v2");
|
