/*
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* Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <fdt_support.h>
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#include <syscon.h>
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#include <linux/libfdt.h>
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#include "../gadget/dwc2_udc_otg_priv.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define BIT_WRITEABLE_SHIFT 16
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struct usb2phy_reg {
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unsigned int offset;
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unsigned int bitend;
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unsigned int bitstart;
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unsigned int disable;
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unsigned int enable;
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};
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/**
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* struct rockchip_usb2_phy_cfg: usb-phy port configuration
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* @port_reset: usb otg per-port reset register
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* @soft_con: software control usb otg register
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* @suspend: phy suspend register
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*/
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struct rockchip_usb2_phy_cfg {
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struct usb2phy_reg port_reset;
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struct usb2phy_reg siddq;
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struct usb2phy_reg soft_con;
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struct usb2phy_reg suspend;
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};
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struct rockchip_usb2_phy_dt_id {
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char compatible[128];
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const void *data;
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};
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static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
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.port_reset = {0x00, 12, 12, 0, 1},
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.siddq = {0x00, 13, 13, 0, 1},
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.soft_con = {0x08, 2, 2, 0, 1},
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.suspend = {0x0c, 5, 0, 0x01, 0x2A},
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};
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static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
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{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
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{}
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};
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static void property_enable(struct dwc2_plat_otg_data *pdata,
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const struct usb2phy_reg *reg, bool en)
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{
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unsigned int val, mask, tmp;
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tmp = en ? reg->enable : reg->disable;
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mask = GENMASK(reg->bitend, reg->bitstart);
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val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
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writel(val, pdata->regs_phy + reg->offset);
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}
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int rockchip_u2phy_vbus_detect(void)
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{
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u32 val = 0;
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#ifdef CONFIG_ROCKCHIP_RK3288
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u32 grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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val = readl(grf_base + 0x288);
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val = (val & BIT(14)) >> 14;
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#endif
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return val;
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}
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static int otg_phy_parse(struct dwc2_udc *dev)
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{
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int node, phy_node;
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u32 grf_base, grf_offset;
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const void *blob = gd->fdt_blob;
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const fdt32_t *reg;
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fdt_addr_t addr;
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struct dwc2_plat_otg_data *pdata = dev->pdata;
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/* Find the usb_otg node */
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node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
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#if defined(CONFIG_ROCKCHIP_RK3288)
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retry:
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#endif
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if (node > 0) {
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reg = fdt_getprop(blob, node, "reg", NULL);
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if (!reg)
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return -EINVAL;
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addr = fdt_translate_address(blob, node, reg);
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if (addr == OF_BAD_ADDR) {
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pr_err("Not found usb_otg address\n");
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return -EINVAL;
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}
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#if defined(CONFIG_ROCKCHIP_RK3288)
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if (addr != 0xff580000) {
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node = fdt_node_offset_by_compatible(blob, node,
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"snps,dwc2");
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goto retry;
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}
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#endif
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} else {
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/*
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* With kernel dtb support, rk3288 dwc2 otg node
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* use the rockchip legacy dwc2 driver "dwc_otg_310"
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* with the compatible "rockchip,rk3288_usb20_otg".
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*/
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#if defined(CONFIG_ROCKCHIP_RK3288)
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node = fdt_node_offset_by_compatible(blob, -1,
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"rockchip,rk3288_usb20_otg");
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#endif
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if (node < 0) {
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pr_err("Not found usb_otg device\n");
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return -ENODEV;
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}
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}
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/* Find the usb phy node */
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node = fdtdec_lookup_phandle(blob, node, "phys");
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if (node <= 0) {
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pr_err("Not found usbphy device\n");
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return -ENODEV;
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}
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/* Find the usb otg-phy node */
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phy_node = fdt_parent_offset(blob, node);
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if (phy_node <= 0) {
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pr_err("Not found sub usbphy device\n");
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return -ENODEV;
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}
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grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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grf_offset = fdtdec_get_addr(blob, node, "reg");
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/* Pad dwc2_plat_otg_data related to phy */
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pdata->phy_of_node = phy_node;
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pdata->regs_phy = grf_base + grf_offset;
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return 0;
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}
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void otg_phy_init(struct dwc2_udc *dev)
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{
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struct dwc2_plat_otg_data *pdata = dev->pdata;
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struct rockchip_usb2_phy_cfg *phy_cfg = NULL;
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struct rockchip_usb2_phy_dt_id *of_id;
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int i;
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if (!pdata->regs_phy && otg_phy_parse(dev)) {
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pr_err("otg-phy parse error\n");
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return;
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}
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for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) {
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of_id = &rockchip_usb2_phy_dt_ids[i];
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if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node,
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of_id->compatible) == 0) {
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phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data;
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break;
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}
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}
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if (!phy_cfg) {
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debug("Can't find device platform data\n");
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hang();
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return;
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}
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pdata->priv = phy_cfg;
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/* power up usb phy analog blocks by set siddq 0 */
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property_enable(pdata, &phy_cfg->siddq, false);
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/* disable software control */
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property_enable(pdata, &phy_cfg->soft_con, false);
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/* reset otg port */
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property_enable(pdata, &phy_cfg->port_reset, true);
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mdelay(1);
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property_enable(pdata, &phy_cfg->port_reset, false);
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udelay(1);
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}
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void otg_phy_off(struct dwc2_udc *dev)
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{
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struct dwc2_plat_otg_data *pdata = dev->pdata;
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struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv;
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if (!pdata->regs_phy && otg_phy_parse(dev)) {
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pr_err("otg-phy parse error\n");
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return;
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}
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/* enable software control */
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property_enable(pdata, &phy_cfg->soft_con, true);
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/* enter suspend */
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property_enable(pdata, &phy_cfg->suspend, true);
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}
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