/*
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* Copyright 2010 Extreme Engineering Solutions, Inc.
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
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{
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i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
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sizeof(ddr3_spd_eeprom_t));
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}
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/*
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* There are traditionally three board-specific SDRAM timing parameters
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* which must be calculated based on the particular PCB artwork. These are:
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* 1.) CPO (Read Capture Delay)
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* - TIMING_CFG_2 register
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* Source: Calculation based on board trace lengths and
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* chip-specific internal delays.
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* 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
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* - DDR_SDRAM_CLK_CNTL register
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* Source: Signal Integrity Simulations
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* 3.) 2T Timing on Addr/Ctl
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* - TIMING_CFG_2 register
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* Source: Signal Integrity Simulations
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* Usually only needed with heavy load/very high speed (>DDR2-800)
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*
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* ====== XPedite550x DDR3-800 read delay calculations ======
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*
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* The P2020 processor provides an autoleveling option. Setting CPO to
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* 0x1f enables this auto configuration.
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*/
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typedef struct {
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unsigned short datarate_mhz_low;
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unsigned short datarate_mhz_high;
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unsigned char clk_adjust;
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unsigned char cpo;
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} board_specific_parameters_t;
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const board_specific_parameters_t board_specific_parameters[][20] = {
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{
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/* Controller 0 */
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{
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/* DDR3-600/667 */
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.datarate_mhz_low = 500,
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.datarate_mhz_high = 750,
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.clk_adjust = 5,
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.cpo = 31,
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},
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{
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/* DDR3-800 */
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.datarate_mhz_low = 750,
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.datarate_mhz_high = 850,
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.clk_adjust = 5,
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.cpo = 31,
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},
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},
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const board_specific_parameters_t *pbsp =
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&(board_specific_parameters[ctrl_num][0]);
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u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
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sizeof(board_specific_parameters[0][0]);
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u32 i;
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ulong ddr_freq;
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/*
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* Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
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* that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
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* there are two dimms in the controller, set odt_rd_cfg to 3 and
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* odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
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*/
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (i&1) { /* odd CS */
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 0;
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} else { /* even CS */
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if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 4;
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} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
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popts->cs_local_opts[i].odt_rd_cfg = 3;
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popts->cs_local_opts[i].odt_wr_cfg = 3;
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}
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}
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}
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/*
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* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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for (i = 0; i < num_params; i++) {
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if (ddr_freq >= pbsp->datarate_mhz_low &&
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ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->twot_en = 0;
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break;
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}
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pbsp++;
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}
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if (i == num_params) {
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printf("Warning: board specific timing not found "
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"for data rate %lu MT/s!\n", ddr_freq);
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}
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/*
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* Enable on-die termination.
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* From the Micron Technical Node TN-41-04, RTT_Nom should typically
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* be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR
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* is handled in the Freescale DDR3 driver. Set RTT_Nom here.
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*/
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popts->rtt_override = 1;
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popts->rtt_override_value = 3;
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}
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