/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
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*
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/libfdt.h>
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#include <pci.h>
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#include <mpc83xx.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <asm/bitops.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void disable_addr_trans (void);
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extern void enable_addr_trans (void);
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int checkboard(void)
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{
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puts("Board: ve8313\n");
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return 0;
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}
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static long fixed_sdram(void)
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{
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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#ifndef CONFIG_SYS_RAMBOOT
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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u32 msize_log2 = __ilog2(msize);
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out_be32(&im->sysconf.ddrlaw[0].bar,
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(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
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out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
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/*
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* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
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* or the DDR2 controller may fail to initialize correctly.
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*/
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__udelay(50000);
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#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
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#warning Chip select bounds is only configurable in 16MB increments
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#endif
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out_be32(&im->ddr.csbnds[0].csbnds,
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((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
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CSBNDS_EA));
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out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
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/* Currently we use only one CS, so disable the other bank. */
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out_be32(&im->ddr.cs_config[1], 0);
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out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
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out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
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out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
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out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
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out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
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out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
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sync();
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/* enable DDR controller */
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
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/* now check the real size */
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disable_addr_trans ();
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msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
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enable_addr_trans ();
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#endif
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return msize;
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}
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int dram_init(void)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile fsl_lbc_t *lbc = &im->im_lbc;
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u32 msize;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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msize = fixed_sdram();
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/* Local Bus setup lbcr and mrtpr */
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out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
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out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
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sync();
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/* return total bus SDRAM size(bytes) -- DDR */
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gd->ram_size = msize;
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return 0;
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}
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#define VE8313_WDT_EN 0x00020000
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#define VE8313_WDT_TRIG 0x00040000
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int board_early_init_f (void)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
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#if defined(CONFIG_HW_WATCHDOG)
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/* enable WDT */
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clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
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#else
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/* disable WDT */
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setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
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#endif
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/* set WDT pins as output */
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setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
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return 0;
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}
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#if defined(CONFIG_HW_WATCHDOG)
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void hw_watchdog_reset(void)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
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unsigned long reg;
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reg = in_be32(&gpio->dat);
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if (reg & VE8313_WDT_TRIG)
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clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
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else
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setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
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}
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#endif
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#if defined(CONFIG_PCI)
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static struct pci_region pci_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI1_MEM_BASE,
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
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size: CONFIG_SYS_PCI1_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
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size: CONFIG_SYS_PCI1_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CONFIG_SYS_PCI1_IO_BASE,
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phys_start: CONFIG_SYS_PCI1_IO_PHYS,
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size: CONFIG_SYS_PCI1_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci_regions };
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/* Enable all 3 PCI_CLK_OUTPUTs. */
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setbits_be32(&clk->occr, 0xe0000000);
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/*
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* Configure PCI Local Access Windows
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*/
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out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
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out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
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out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
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out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
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mpc83xx_pci_init(1, reg);
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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#endif
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