/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
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* Author: Markus Niebel <markus.niebel@tq-group.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <linux/libfdt.h>
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#include <malloc.h>
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#include <i2c.h>
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#include <micrel.h>
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#include <miiphy.h>
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#include <mmc.h>
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#include <netdev.h>
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#include "tqma6_bb.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#if defined(CONFIG_TQMA6Q)
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#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
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#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
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#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
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#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
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#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
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#else
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#error "need to select module"
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#endif
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#define ENET_RX_PAD_CTRL (PAD_CTL_DSE_34ohm)
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#define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_34ohm)
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#define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_60ohm)
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/* disable on die termination for RGMII */
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#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000
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/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
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#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000
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/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
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#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000
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#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25)
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static iomux_v3_cfg_t const mba6_enet_pads[] = {
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NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_MDIO_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_MDIO_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_TX_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_TX_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_TX_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_TX_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_TX_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL,
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ENET_TX_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL),
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/*
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* these pins are also used for config strapping by phy
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*/
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NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_RX_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_RX_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_RX_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_RX_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_RX_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL,
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ENET_RX_PAD_CTRL),
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/* KSZ9031 PHY Reset */
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NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25, GPIO_OUT_PAD_CTRL),
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};
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static void mba6_setup_iomuxc_enet(void)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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/* clear gpr1[ENET_CLK_SEL] for externel clock */
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clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
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__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
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(void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
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__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
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(void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
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imx_iomux_v3_setup_multiple_pads(mba6_enet_pads,
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ARRAY_SIZE(mba6_enet_pads));
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/* Reset PHY */
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gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
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/* Need delay 10ms after power on according to KSZ9031 spec */
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mdelay(10);
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gpio_set_value(ENET_PHY_RESET_GPIO, 1);
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/*
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* KSZ9031 manual: 100 usec wait time after reset before communication
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* over MDIO
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* BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
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* reset before the phy sees a high level
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*/
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mdelay(15);
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}
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static iomux_v3_cfg_t const mba6_uart2_pads[] = {
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NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
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};
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static void mba6_setup_iomuxc_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
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ARRAY_SIZE(mba6_uart2_pads));
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}
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#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
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#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
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int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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if (cfg->esdhc_base == USDHC2_BASE_ADDR)
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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return ret;
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}
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int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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if (cfg->esdhc_base == USDHC2_BASE_ADDR)
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ret = gpio_get_value(USDHC2_WP_GPIO);
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return ret;
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}
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static struct fsl_esdhc_cfg mba6_usdhc_cfg = {
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.esdhc_base = USDHC2_BASE_ADDR,
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.max_bus_width = 4,
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};
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static iomux_v3_cfg_t const mba6_usdhc2_pads[] = {
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NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC_CLK_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
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/* CD */
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NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, GPIO_IN_PAD_CTRL),
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/* WP */
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NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02, GPIO_IN_PAD_CTRL),
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};
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int tqma6_bb_board_mmc_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads,
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ARRAY_SIZE(mba6_usdhc2_pads));
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gpio_direction_input(USDHC2_CD_GPIO);
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gpio_direction_input(USDHC2_WP_GPIO);
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mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg))
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puts("Warning: failed to initialize SD\n");
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return 0;
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}
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static struct i2c_pads_info mba6_i2c1_pads = {
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/* I2C1: MBa6x */
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.scl = {
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.i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL,
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I2C_PAD_CTRL),
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.gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27,
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I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(5, 27)
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},
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.sda = {
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.i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA,
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I2C_PAD_CTRL),
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.gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26,
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I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(5, 26)
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}
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};
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static void mba6_setup_i2c(void)
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{
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int ret;
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/*
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* use logical index for bus, e.g. I2C1 -> 0
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* warn on error
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*/
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ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
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if (ret)
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printf("setup I2C1 failed: %d\n", ret);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/*
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* optimized pad skew values depends on CPU variant on the TQMa6x module:
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* CONFIG_TQMA6Q: i.MX6Q/D
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* CONFIG_TQMA6S: i.MX6S
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* CONFIG_TQMA6DL: i.MX6DL
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*/
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#if defined(CONFIG_TQMA6Q)
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#define MBA6X_KSZ9031_CTRL_SKEW 0x0032
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#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
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#define MBA6X_KSZ9031_RX_SKEW 0x3333
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#define MBA6X_KSZ9031_TX_SKEW 0x2036
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#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
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#define MBA6X_KSZ9031_CTRL_SKEW 0x0030
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#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
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#define MBA6X_KSZ9031_RX_SKEW 0x3333
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#define MBA6X_KSZ9031_TX_SKEW 0x2052
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#else
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#error
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#endif
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/* min rx/tx ctrl delay */
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ksz9031_phy_extended_write(phydev, 2,
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MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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MBA6X_KSZ9031_CTRL_SKEW);
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/* min rx delay */
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ksz9031_phy_extended_write(phydev, 2,
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MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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MBA6X_KSZ9031_RX_SKEW);
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/* max tx delay */
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ksz9031_phy_extended_write(phydev, 2,
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MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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MBA6X_KSZ9031_TX_SKEW);
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/* rx/tx clk skew */
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ksz9031_phy_extended_write(phydev, 2,
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MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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MBA6X_KSZ9031_CLK_SKEW);
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phydev->drv->config(phydev);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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uint32_t base = IMX_FEC_BASE;
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struct mii_dev *bus = NULL;
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struct phy_device *phydev = NULL;
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int ret;
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bus = fec_get_miibus(base, -1);
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if (!bus)
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return -EINVAL;
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/* scan phy */
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phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
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PHY_INTERFACE_MODE_RGMII);
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if (!phydev) {
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ret = -EINVAL;
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goto free_bus;
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}
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ret = fec_probe(bis, -1, base, bus, phydev);
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if (ret)
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goto free_phydev;
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return 0;
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free_phydev:
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free(phydev);
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free_bus:
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free(bus);
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return ret;
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}
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int tqma6_bb_board_early_init_f(void)
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{
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mba6_setup_iomuxc_uart();
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return 0;
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}
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int tqma6_bb_board_init(void)
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{
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mba6_setup_i2c();
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/* do it here - to have reset completed */
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mba6_setup_iomuxc_enet();
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return 0;
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}
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int tqma6_bb_board_late_init(void)
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{
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return 0;
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}
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const char *tqma6_bb_get_boardname(void)
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{
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return "MBa6x";
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}
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/*
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* Device Tree Support
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*/
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
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{
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/* TBD */
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}
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#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
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