/*
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* Copyright (C) 2014-2016, Toradex AG
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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// Register Output for PF0100 programmer
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// Customer: Toradex AG
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// Program: Apalis iMX6
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// Sample marking:
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// Date: 12.02.2014
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// Time: 17:16:41
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// Generated from Spreadsheet Revision: P1.8
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/* sed commands to get from programmer script to struct */
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/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc
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sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
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sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
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enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
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struct pmic_otp_prog_t{
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unsigned char cmd;
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unsigned char reg;
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unsigned short value;
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};
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struct pmic_otp_prog_t pmic_otp_prog[] = {
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{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
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{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
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{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
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{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
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{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
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{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
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{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
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{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
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{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
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{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
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{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
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{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
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{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
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{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
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{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
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{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
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{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
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{pmic_i2c, 0xBD, 0x1F}, // Auto gen from Row123
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{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
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{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
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{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
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{pmic_i2c, 0xC9, 0x08}, // Auto gen from Row135
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{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
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{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
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{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
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{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
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{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
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{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
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{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
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{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
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{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
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{pmic_i2c, 0xE0, 0x07}, // Auto gen from Row158
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#if 0 /* TBB mode */
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{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
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{pmic_delay, 0, 10},
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#else
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// Write OTP
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{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
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{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
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{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
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{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
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{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
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{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
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{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
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{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
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//-----------------------------------------------------------------------------------
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{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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//-----------------------------------------------------------------------------------
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{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
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//VPGM:DOWN:n
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//VPGM:UP:n
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{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
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//-----------------------------------------------------------------------------------
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// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
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//-----------------------------------------------------------------------------------
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// BANK 1
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//-----------------------------------------------------------------------------------
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{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
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{pmic_delay, 0, 10}, // Allow time for bank programming to complete
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{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
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{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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//-----------------------------------------------------------------------------------
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// BANK 2
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//-----------------------------------------------------------------------------------
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{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
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{pmic_delay, 0, 10}, // Allow time for bank programming to complete
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{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
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{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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//-----------------------------------------------------------------------------------
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// BANK 3
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//-----------------------------------------------------------------------------------
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{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
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{pmic_delay, 0, 10}, // Allow time for bank programming to complete
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{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
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{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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//-----------------------------------------------------------------------------------
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// BANK 4
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//-----------------------------------------------------------------------------------
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{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
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{pmic_delay, 0, 10}, // Allow time for bank programming to complete
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{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
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{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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//-----------------------------------------------------------------------------------
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// BANK 5
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//-----------------------------------------------------------------------------------
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{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
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{pmic_delay, 0, 10}, // Allow time for bank programming to complete
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{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
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{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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//-----------------------------------------------------------------------------------
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// BANK 6
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//-----------------------------------------------------------------------------------
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{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
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{pmic_delay, 0, 10}, // Allow time for bank programming to complete
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{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
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{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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//-----------------------------------------------------------------------------------
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// BANK 7
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//-----------------------------------------------------------------------------------
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{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
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{pmic_delay, 0, 10}, // Allow time for bank programming to complete
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{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
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{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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//-----------------------------------------------------------------------------------
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// BANK 8
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//-----------------------------------------------------------------------------------
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{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
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{pmic_delay, 0, 10}, // Allow time for bank programming to complete
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{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
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{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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//-----------------------------------------------------------------------------------
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// BANK 9
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//-----------------------------------------------------------------------------------
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{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
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{pmic_delay, 0, 10}, // Allow time for bank programming to complete
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{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
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{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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//-----------------------------------------------------------------------------------
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// BANK 10
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//-----------------------------------------------------------------------------------
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{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
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{pmic_delay, 0, 10}, // Allow time for bank programming to complete
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{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
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{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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//-----------------------------------------------------------------------------------
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{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
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{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
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{pmic_i2c, 0xD0, 0x00}, // Clear
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{pmic_i2c, 0xD1, 0x00}, // Clear
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{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
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{pmic_delay, 0, 500},
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{pmic_pwr, 0, 1},
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#endif
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};
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