/*
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* (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
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* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Some board init for the Allwinner A10-evb board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mmc.h>
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#include <axp_pmic.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/display.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/spl.h>
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#include <asm/arch/usb_phy.h>
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#ifndef CONFIG_ARM64
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#include <asm/armv7.h>
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#endif
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <crc.h>
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#include <environment.h>
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#include <linux/libfdt.h>
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#include <nand.h>
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#include <net.h>
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#include <sy8106a.h>
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#include <asm/setup.h>
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#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
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/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
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int soft_i2c_gpio_sda;
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int soft_i2c_gpio_scl;
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static int soft_i2c_board_init(void)
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{
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int ret;
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soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
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if (soft_i2c_gpio_sda < 0) {
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printf("Error invalid soft i2c sda pin: '%s', err %d\n",
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CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
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return soft_i2c_gpio_sda;
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}
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ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
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if (ret) {
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printf("Error requesting soft i2c sda pin: '%s', err %d\n",
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CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
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return ret;
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}
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soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
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if (soft_i2c_gpio_scl < 0) {
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printf("Error invalid soft i2c scl pin: '%s', err %d\n",
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CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
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return soft_i2c_gpio_scl;
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}
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ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
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if (ret) {
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printf("Error requesting soft i2c scl pin: '%s', err %d\n",
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CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
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return ret;
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}
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return 0;
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}
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#else
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static int soft_i2c_board_init(void) { return 0; }
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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void i2c_init_board(void)
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{
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#ifdef CONFIG_I2C0_ENABLE
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#if defined(CONFIG_MACH_SUN4I) || \
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defined(CONFIG_MACH_SUN5I) || \
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defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_R40)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
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clock_twi_onoff(0, 1);
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#elif defined(CONFIG_MACH_SUN6I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
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clock_twi_onoff(0, 1);
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#elif defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
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clock_twi_onoff(0, 1);
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#endif
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#endif
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#ifdef CONFIG_I2C1_ENABLE
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#if defined(CONFIG_MACH_SUN4I) || \
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defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_R40)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
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clock_twi_onoff(1, 1);
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#elif defined(CONFIG_MACH_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
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clock_twi_onoff(1, 1);
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#elif defined(CONFIG_MACH_SUN6I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
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clock_twi_onoff(1, 1);
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#elif defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
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clock_twi_onoff(1, 1);
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#endif
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#endif
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#ifdef CONFIG_I2C2_ENABLE
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#if defined(CONFIG_MACH_SUN4I) || \
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defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_R40)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
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clock_twi_onoff(2, 1);
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#elif defined(CONFIG_MACH_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
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clock_twi_onoff(2, 1);
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#elif defined(CONFIG_MACH_SUN6I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
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clock_twi_onoff(2, 1);
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#elif defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
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sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
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clock_twi_onoff(2, 1);
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#endif
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#endif
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#ifdef CONFIG_I2C3_ENABLE
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#if defined(CONFIG_MACH_SUN6I)
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sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
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sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
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clock_twi_onoff(3, 1);
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#elif defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_R40)
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sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
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sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
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clock_twi_onoff(3, 1);
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#endif
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#endif
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#ifdef CONFIG_I2C4_ENABLE
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#if defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_R40)
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sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
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sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
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clock_twi_onoff(4, 1);
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#endif
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#endif
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#ifdef CONFIG_R_I2C_ENABLE
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clock_twi_onoff(5, 1);
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sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
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sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
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#endif
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}
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/* add board specific code here */
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int board_init(void)
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{
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__maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
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gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
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#ifndef CONFIG_ARM64
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asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
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debug("id_pfr1: 0x%08x\n", id_pfr1);
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/* Generic Timer Extension available? */
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if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
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uint32_t freq;
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debug("Setting CNTFRQ\n");
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/*
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* CNTFRQ is a secure register, so we will crash if we try to
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* write this from the non-secure world (read is OK, though).
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* In case some bootcode has already set the correct value,
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* we avoid the risk of writing to it.
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*/
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asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
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if (freq != COUNTER_FREQUENCY) {
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debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
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freq, COUNTER_FREQUENCY);
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#ifdef CONFIG_NON_SECURE
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printf("arch timer frequency is wrong, but cannot adjust it\n");
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#else
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asm volatile("mcr p15, 0, %0, c14, c0, 0"
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: : "r"(COUNTER_FREQUENCY));
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#endif
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}
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}
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#endif /* !CONFIG_ARM64 */
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ret = axp_gpio_init();
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if (ret)
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return ret;
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#ifdef CONFIG_SATAPWR
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satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
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gpio_request(satapwr_pin, "satapwr");
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gpio_direction_output(satapwr_pin, 1);
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#endif
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#ifdef CONFIG_MACPWR
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macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
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gpio_request(macpwr_pin, "macpwr");
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gpio_direction_output(macpwr_pin, 1);
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#endif
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#ifdef CONFIG_DM_I2C
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/*
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* Temporary workaround for enabling I2C clocks until proper sunxi DM
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* clk, reset and pinctrl drivers land.
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*/
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i2c_init_board();
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#endif
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/* Uses dm gpio code so do this here and not in i2c_init_board() */
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return soft_i2c_board_init();
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
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return 0;
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}
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#if defined(CONFIG_NAND_SUNXI)
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static void nand_pinmux_setup(void)
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{
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unsigned int pin;
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for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
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#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
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for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
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#endif
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/* sun4i / sun7i do have a PC23, but it is not used for nand,
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* only sun7i has a PC24 */
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#ifdef CONFIG_MACH_SUN7I
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sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
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#endif
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}
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static void nand_clock_setup(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
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#ifdef CONFIG_MACH_SUN9I
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setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
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#else
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setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
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#endif
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setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
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}
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void board_nand_init(void)
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{
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nand_pinmux_setup();
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nand_clock_setup();
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#ifndef CONFIG_SPL_BUILD
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sunxi_nand_init();
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#endif
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}
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#endif
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#ifdef CONFIG_MMC
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static void mmc_pinmux_setup(int sdc)
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{
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unsigned int pin;
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__maybe_unused int pins;
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switch (sdc) {
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case 0:
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/* SDC0: PF0-PF5 */
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for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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break;
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case 1:
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pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
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#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_R40)
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if (pins == SUNXI_GPIO_H) {
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/* SDC1: PH22-PH-27 */
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for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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} else {
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/* SDC1: PG0-PG5 */
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for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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}
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#elif defined(CONFIG_MACH_SUN5I)
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/* SDC1: PG3-PG8 */
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for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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#elif defined(CONFIG_MACH_SUN6I)
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/* SDC1: PG0-PG5 */
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for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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#elif defined(CONFIG_MACH_SUN8I)
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if (pins == SUNXI_GPIO_D) {
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/* SDC1: PD2-PD7 */
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for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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} else {
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/* SDC1: PG0-PG5 */
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for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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}
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#endif
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break;
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case 2:
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pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
|
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#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
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/* SDC2: PC6-PC11 */
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for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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#elif defined(CONFIG_MACH_SUN5I)
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if (pins == SUNXI_GPIO_E) {
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/* SDC2: PE4-PE9 */
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for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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} else {
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/* SDC2: PC6-PC15 */
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for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
|
}
|
#elif defined(CONFIG_MACH_SUN6I)
|
if (pins == SUNXI_GPIO_A) {
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/* SDC2: PA9-PA14 */
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for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
|
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
|
}
|
} else {
|
/* SDC2: PC6-PC15, PC24 */
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for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
|
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
|
}
|
|
sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
|
sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
|
sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
|
}
|
#elif defined(CONFIG_MACH_SUN8I_R40)
|
/* SDC2: PC6-PC15, PC24 */
|
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
|
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
|
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
|
sunxi_gpio_set_drv(pin, 2);
|
}
|
|
sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
|
sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
|
sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
|
#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
|
/* SDC2: PC5-PC6, PC8-PC16 */
|
for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
|
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
|
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
|
sunxi_gpio_set_drv(pin, 2);
|
}
|
|
for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
|
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
|
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
|
sunxi_gpio_set_drv(pin, 2);
|
}
|
#elif defined(CONFIG_MACH_SUN9I)
|
/* SDC2: PC6-PC16 */
|
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
|
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
|
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
|
sunxi_gpio_set_drv(pin, 2);
|
}
|
#endif
|
break;
|
|
case 3:
|
pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
|
|
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
|
defined(CONFIG_MACH_SUN8I_R40)
|
/* SDC3: PI4-PI9 */
|
for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
|
sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
|
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
|
sunxi_gpio_set_drv(pin, 2);
|
}
|
#elif defined(CONFIG_MACH_SUN6I)
|
if (pins == SUNXI_GPIO_A) {
|
/* SDC3: PA9-PA14 */
|
for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
|
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
|
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
|
sunxi_gpio_set_drv(pin, 2);
|
}
|
} else {
|
/* SDC3: PC6-PC15, PC24 */
|
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
|
sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
|
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
|
sunxi_gpio_set_drv(pin, 2);
|
}
|
|
sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
|
sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
|
sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
|
}
|
#endif
|
break;
|
|
default:
|
printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
|
break;
|
}
|
}
|
|
int board_mmc_init(bd_t *bis)
|
{
|
__maybe_unused struct mmc *mmc0, *mmc1;
|
__maybe_unused char buf[512];
|
|
mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
|
mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
|
if (!mmc0)
|
return -1;
|
|
#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
|
mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
|
mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
|
if (!mmc1)
|
return -1;
|
#endif
|
|
#if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
|
/*
|
* On systems with an emmc (mmc2), figure out if we are booting from
|
* the emmc and if we are make it "mmc dev 0" so that boot.scr, etc.
|
* are searched there first. Note we only do this for u-boot proper,
|
* not for the SPL, see spl_boot_device().
|
*/
|
if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) {
|
/* Booting from emmc / mmc2, swap */
|
mmc0->block_dev.devnum = 1;
|
mmc1->block_dev.devnum = 0;
|
}
|
#endif
|
|
return 0;
|
}
|
#endif
|
|
#ifdef CONFIG_SPL_BUILD
|
void sunxi_board_init(void)
|
{
|
int power_failed = 0;
|
|
#ifdef CONFIG_SY8106A_POWER
|
power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
|
#endif
|
|
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
|
defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
|
defined CONFIG_AXP818_POWER
|
power_failed = axp_init();
|
|
#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
|
defined CONFIG_AXP818_POWER
|
power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
|
#endif
|
power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
|
power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
|
#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
|
power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
|
#endif
|
#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
|
defined CONFIG_AXP818_POWER
|
power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
|
#endif
|
|
#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
|
defined CONFIG_AXP818_POWER
|
power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
|
#endif
|
power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
|
#if !defined(CONFIG_AXP152_POWER)
|
power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
|
#endif
|
#ifdef CONFIG_AXP209_POWER
|
power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
|
#endif
|
|
#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
|
defined(CONFIG_AXP818_POWER)
|
power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
|
power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
|
#if !defined CONFIG_AXP809_POWER
|
power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
|
power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
|
#endif
|
power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
|
power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
|
power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
|
#endif
|
|
#ifdef CONFIG_AXP818_POWER
|
power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
|
power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
|
power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
|
#endif
|
|
#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
|
power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
|
#endif
|
#endif
|
printf("DRAM:");
|
gd->ram_size = sunxi_dram_init();
|
printf(" %d MiB\n", (int)(gd->ram_size >> 20));
|
if (!gd->ram_size)
|
hang();
|
|
/*
|
* Only clock up the CPU to full speed if we are reasonably
|
* assured it's being powered with suitable core voltage
|
*/
|
if (!power_failed)
|
clock_set_pll1(CONFIG_SYS_CLK_FREQ);
|
else
|
printf("Failed to set core voltage! Can't set CPU frequency\n");
|
}
|
#endif
|
|
#ifdef CONFIG_USB_GADGET
|
int g_dnl_board_usb_cable_connected(void)
|
{
|
struct udevice *dev;
|
struct phy phy;
|
int ret;
|
|
ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
|
if (ret) {
|
pr_err("%s: Cannot find USB device\n", __func__);
|
return ret;
|
}
|
|
ret = generic_phy_get_by_name(dev, "usb", &phy);
|
if (ret) {
|
pr_err("failed to get %s USB PHY\n", dev->name);
|
return ret;
|
}
|
|
ret = generic_phy_init(&phy);
|
if (ret) {
|
pr_err("failed to init %s USB PHY\n", dev->name);
|
return ret;
|
}
|
|
ret = sun4i_usb_phy_vbus_detect(&phy);
|
if (ret == 1) {
|
pr_err("A charger is plugged into the OTG\n");
|
return -ENODEV;
|
}
|
|
return ret;
|
}
|
#endif
|
|
#ifdef CONFIG_SERIAL_TAG
|
void get_board_serial(struct tag_serialnr *serialnr)
|
{
|
char *serial_string;
|
unsigned long long serial;
|
|
serial_string = env_get("serial#");
|
|
if (serial_string) {
|
serial = simple_strtoull(serial_string, NULL, 16);
|
|
serialnr->high = (unsigned int) (serial >> 32);
|
serialnr->low = (unsigned int) (serial & 0xffffffff);
|
} else {
|
serialnr->high = 0;
|
serialnr->low = 0;
|
}
|
}
|
#endif
|
|
/*
|
* Check the SPL header for the "sunxi" variant. If found: parse values
|
* that might have been passed by the loader ("fel" utility), and update
|
* the environment accordingly.
|
*/
|
static void parse_spl_header(const uint32_t spl_addr)
|
{
|
struct boot_file_head *spl = (void *)(ulong)spl_addr;
|
if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
|
return; /* signature mismatch, no usable header */
|
|
uint8_t spl_header_version = spl->spl_signature[3];
|
if (spl_header_version != SPL_HEADER_VERSION) {
|
printf("sunxi SPL version mismatch: expected %u, got %u\n",
|
SPL_HEADER_VERSION, spl_header_version);
|
return;
|
}
|
if (!spl->fel_script_address)
|
return;
|
|
if (spl->fel_uEnv_length != 0) {
|
/*
|
* data is expected in uEnv.txt compatible format, so "env
|
* import -t" the string(s) at fel_script_address right away.
|
*/
|
himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
|
spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
|
return;
|
}
|
/* otherwise assume .scr format (mkimage-type script) */
|
env_set_hex("fel_scriptaddr", spl->fel_script_address);
|
}
|
|
/*
|
* Note this function gets called multiple times.
|
* It must not make any changes to env variables which already exist.
|
*/
|
static void setup_environment(const void *fdt)
|
{
|
char serial_string[17] = { 0 };
|
unsigned int sid[4];
|
uint8_t mac_addr[6];
|
char ethaddr[16];
|
int i, ret;
|
|
ret = sunxi_get_sid(sid);
|
if (ret == 0 && sid[0] != 0) {
|
/*
|
* The single words 1 - 3 of the SID have quite a few bits
|
* which are the same on many models, so we take a crc32
|
* of all 3 words, to get a more unique value.
|
*
|
* Note we only do this on newer SoCs as we cannot change
|
* the algorithm on older SoCs since those have been using
|
* fixed mac-addresses based on only using word 3 for a
|
* long time and changing a fixed mac-address with an
|
* u-boot update is not good.
|
*/
|
#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
|
!defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
|
!defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
|
sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
|
#endif
|
|
/* Ensure the NIC specific bytes of the mac are not all 0 */
|
if ((sid[3] & 0xffffff) == 0)
|
sid[3] |= 0x800000;
|
|
for (i = 0; i < 4; i++) {
|
sprintf(ethaddr, "ethernet%d", i);
|
if (!fdt_get_alias(fdt, ethaddr))
|
continue;
|
|
if (i == 0)
|
strcpy(ethaddr, "ethaddr");
|
else
|
sprintf(ethaddr, "eth%daddr", i);
|
|
if (env_get(ethaddr))
|
continue;
|
|
/* Non OUI / registered MAC address */
|
mac_addr[0] = (i << 4) | 0x02;
|
mac_addr[1] = (sid[0] >> 0) & 0xff;
|
mac_addr[2] = (sid[3] >> 24) & 0xff;
|
mac_addr[3] = (sid[3] >> 16) & 0xff;
|
mac_addr[4] = (sid[3] >> 8) & 0xff;
|
mac_addr[5] = (sid[3] >> 0) & 0xff;
|
|
eth_env_set_enetaddr(ethaddr, mac_addr);
|
}
|
|
if (!env_get("serial#")) {
|
snprintf(serial_string, sizeof(serial_string),
|
"%08x%08x", sid[0], sid[3]);
|
|
env_set("serial#", serial_string);
|
}
|
}
|
}
|
|
int misc_init_r(void)
|
{
|
__maybe_unused int ret;
|
|
env_set("fel_booted", NULL);
|
env_set("fel_scriptaddr", NULL);
|
/* determine if we are running in FEL mode */
|
if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
|
env_set("fel_booted", "1");
|
parse_spl_header(SPL_ADDR);
|
}
|
|
setup_environment(gd->fdt_blob);
|
|
#ifndef CONFIG_MACH_SUN9I
|
ret = sunxi_usb_phy_probe();
|
if (ret)
|
return ret;
|
#endif
|
|
return 0;
|
}
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
{
|
int __maybe_unused r;
|
|
/*
|
* Call setup_environment again in case the boot fdt has
|
* ethernet aliases the u-boot copy does not have.
|
*/
|
setup_environment(blob);
|
|
#ifdef CONFIG_VIDEO_DT_SIMPLEFB
|
r = sunxi_simplefb_setup(blob);
|
if (r)
|
return r;
|
#endif
|
return 0;
|
}
|
|
#ifdef CONFIG_SPL_LOAD_FIT
|
int board_fit_config_name_match(const char *name)
|
{
|
struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
|
const char *cmp_str = (void *)(ulong)SPL_ADDR;
|
|
/* Check if there is a DT name stored in the SPL header and use that. */
|
if (spl->dt_name_offset) {
|
cmp_str += spl->dt_name_offset;
|
} else {
|
#ifdef CONFIG_DEFAULT_DEVICE_TREE
|
cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
|
#else
|
return 0;
|
#endif
|
};
|
|
/* Differentiate the two Pine64 board DTs by their DRAM size. */
|
if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
|
if ((gd->ram_size > 512 * 1024 * 1024))
|
return !strstr(name, "plus");
|
else
|
return !!strstr(name, "plus");
|
} else {
|
return strcmp(name, cmp_str);
|
}
|
}
|
#endif
|
