// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <adc.h>
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#include <config.h>
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#include <clk.h>
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#include <dm.h>
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#include <g_dnl.h>
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#include <generic-phy.h>
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#include <i2c.h>
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#include <led.h>
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#include <misc.h>
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#include <mtd.h>
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#include <mtd_node.h>
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#include <netdev.h>
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#include <phy.h>
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#include <reset.h>
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#include <syscon.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/stm32.h>
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#include <power/regulator.h>
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#include <usb/dwc2_udc.h>
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/* SYSCFG registers */
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#define SYSCFG_BOOTR 0x00
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#define SYSCFG_PMCSETR 0x04
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#define SYSCFG_IOCTRLSETR 0x18
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#define SYSCFG_ICNR 0x1C
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#define SYSCFG_CMPCR 0x20
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#define SYSCFG_CMPENSETR 0x24
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#define SYSCFG_PMCCLRR 0x44
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#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
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#define SYSCFG_BOOTR_BOOTPD_SHIFT 4
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#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
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#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
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#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
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#define SYSCFG_CMPCR_SW_CTRL BIT(1)
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#define SYSCFG_CMPCR_READY BIT(8)
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#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
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#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
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#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
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#define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
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#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
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#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII (0 << 21)
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#define SYSCFG_PMCSETR_ETH_SEL_RGMII (1 << 21)
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#define SYSCFG_PMCSETR_ETH_SEL_RMII (4 << 21)
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/*
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* Get a global data pointer
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*/
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DECLARE_GLOBAL_DATA_PTR;
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#define USB_WARNING_LOW_THRESHOLD_UV 660000
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#define USB_START_LOW_THRESHOLD_UV 1230000
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#define USB_START_HIGH_THRESHOLD_UV 2100000
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int checkboard(void)
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{
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int ret;
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char *mode;
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u32 otp;
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struct udevice *dev;
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const char *fdt_compat;
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int fdt_compat_len;
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if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED))
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mode = "trusted";
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else
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mode = "basic";
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printf("Board: stm32mp1 in %s mode", mode);
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fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
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&fdt_compat_len);
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if (fdt_compat && fdt_compat_len)
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printf(" (%s)", fdt_compat);
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puts("\n");
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(stm32mp_bsec),
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&dev);
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if (!ret)
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ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
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&otp, sizeof(otp));
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if (!ret && otp) {
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printf("Board: MB%04x Var%d Rev.%c-%02d\n",
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otp >> 16,
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(otp >> 12) & 0xF,
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((otp >> 8) & 0xF) - 1 + 'A',
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otp & 0xF);
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}
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return 0;
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}
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static void board_key_check(void)
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{
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#if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
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ofnode node;
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struct gpio_desc gpio;
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enum forced_boot_mode boot_mode = BOOT_NORMAL;
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node = ofnode_path("/config");
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if (!ofnode_valid(node)) {
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debug("%s: no /config node?\n", __func__);
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return;
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}
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#ifdef CONFIG_FASTBOOT
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if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
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&gpio, GPIOD_IS_IN)) {
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debug("%s: could not find a /config/st,fastboot-gpios\n",
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__func__);
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} else {
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if (dm_gpio_get_value(&gpio)) {
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puts("Fastboot key pressed, ");
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boot_mode = BOOT_FASTBOOT;
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}
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dm_gpio_free(NULL, &gpio);
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}
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#endif
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#ifdef CONFIG_CMD_STM32PROG
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if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
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&gpio, GPIOD_IS_IN)) {
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debug("%s: could not find a /config/st,stm32prog-gpios\n",
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__func__);
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} else {
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if (dm_gpio_get_value(&gpio)) {
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puts("STM32Programmer key pressed, ");
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boot_mode = BOOT_STM32PROG;
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}
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dm_gpio_free(NULL, &gpio);
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}
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#endif
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if (boot_mode != BOOT_NORMAL) {
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puts("entering download mode...\n");
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clrsetbits_le32(TAMP_BOOT_CONTEXT,
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TAMP_BOOT_FORCED_MASK,
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boot_mode);
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}
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#endif
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}
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#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
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/* STMicroelectronics STUSB1600 Type-C controller */
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#define STUSB1600_CC_CONNECTION_STATUS 0x0E
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/* STUSB1600_CC_CONNECTION_STATUS bitfields */
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#define STUSB1600_CC_ATTACH BIT(0)
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static int stusb1600_init(struct udevice **dev_stusb1600)
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{
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ofnode node;
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struct udevice *dev, *bus;
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int ret;
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u32 chip_addr;
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*dev_stusb1600 = NULL;
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/* if node stusb1600 is present, means DK1 or DK2 board */
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node = ofnode_by_compatible(ofnode_null(), "st,stusb1600");
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if (!ofnode_valid(node))
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return -ENODEV;
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ret = ofnode_read_u32(node, "reg", &chip_addr);
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if (ret)
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return -EINVAL;
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ret = uclass_get_device_by_ofnode(UCLASS_I2C, ofnode_get_parent(node),
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&bus);
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if (ret) {
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printf("bus for stusb1600 not found\n");
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return -ENODEV;
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}
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ret = dm_i2c_probe(bus, chip_addr, 0, &dev);
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if (!ret)
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*dev_stusb1600 = dev;
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return ret;
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}
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static int stusb1600_cable_connected(struct udevice *dev)
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{
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u8 status;
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if (dm_i2c_read(dev, STUSB1600_CC_CONNECTION_STATUS, &status, 1))
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return 0;
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return status & STUSB1600_CC_ATTACH;
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}
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#include <usb/dwc2_udc.h>
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int g_dnl_board_usb_cable_connected(void)
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{
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struct udevice *stusb1600;
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struct udevice *dwc2_udc_otg;
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int ret;
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if (!stusb1600_init(&stusb1600))
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return stusb1600_cable_connected(stusb1600);
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ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
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DM_GET_DRIVER(dwc2_udc_otg),
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&dwc2_udc_otg);
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if (!ret)
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debug("dwc2_udc_otg init failed\n");
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return dwc2_udc_B_session_valid(dwc2_udc_otg);
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}
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#endif /* CONFIG_USB_GADGET */
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static int get_led(struct udevice **dev, char *led_string)
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{
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char *led_name;
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int ret;
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led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
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if (!led_name) {
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pr_debug("%s: could not find %s config string\n",
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__func__, led_string);
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return -ENOENT;
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}
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ret = led_get_by_label(led_name, dev);
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if (ret) {
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debug("%s: get=%d\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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static int setup_led(enum led_state_t cmd)
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{
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struct udevice *dev;
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int ret;
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ret = get_led(&dev, "u-boot,boot-led");
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if (ret)
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return ret;
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ret = led_set_state(dev, cmd);
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return ret;
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}
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static int board_check_usb_power(void)
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{
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struct ofnode_phandle_args adc_args;
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struct udevice *adc;
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struct udevice *led;
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ofnode node;
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unsigned int raw;
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int max_uV = 0;
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int ret, uV, adc_count;
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u8 i, nb_blink;
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node = ofnode_path("/config");
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if (!ofnode_valid(node)) {
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debug("%s: no /config node?\n", __func__);
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return -ENOENT;
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}
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/*
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* Retrieve the ADC channels devices and get measurement
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* for each of them
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*/
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adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd",
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"#io-channel-cells");
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if (adc_count < 0) {
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if (adc_count == -ENOENT)
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return 0;
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pr_err("%s: can't find adc channel (%d)\n", __func__,
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adc_count);
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return adc_count;
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}
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for (i = 0; i < adc_count; i++) {
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if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
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"#io-channel-cells", 0, i,
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&adc_args)) {
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pr_debug("%s: can't find /config/st,adc_usb_pd\n",
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__func__);
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return 0;
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}
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ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node,
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&adc);
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if (ret) {
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pr_err("%s: Can't get adc device(%d)\n", __func__,
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ret);
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return ret;
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}
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ret = adc_channel_single_shot(adc->name, adc_args.args[0],
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&raw);
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if (ret) {
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pr_err("%s: single shot failed for %s[%d]!\n",
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__func__, adc->name, adc_args.args[0]);
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return ret;
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}
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/* Convert to uV */
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if (!adc_raw_to_uV(adc, raw, &uV)) {
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if (uV > max_uV)
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max_uV = uV;
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pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__,
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adc->name, adc_args.args[0], raw, uV);
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} else {
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pr_err("%s: Can't get uV value for %s[%d]\n",
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__func__, adc->name, adc_args.args[0]);
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}
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}
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/*
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* If highest value is inside 1.23 Volts and 2.10 Volts, that means
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* board is plugged on an USB-C 3A power supply and boot process can
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* continue.
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*/
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if (max_uV > USB_START_LOW_THRESHOLD_UV &&
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max_uV < USB_START_HIGH_THRESHOLD_UV)
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return 0;
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/* Display warning message and make u-boot,error-led blinking */
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pr_err("\n*******************************************\n");
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if (max_uV < USB_WARNING_LOW_THRESHOLD_UV) {
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pr_err("* WARNING 500mA power supply detected *\n");
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nb_blink = 2;
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} else {
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pr_err("* WARNING 1.5A power supply detected *\n");
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nb_blink = 3;
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}
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pr_err("* Current too low, use a 3A power supply! *\n");
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pr_err("*******************************************\n\n");
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ret = get_led(&led, "u-boot,error-led");
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if (ret)
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return ret;
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for (i = 0; i < nb_blink * 2; i++) {
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led_set_state(led, LEDST_TOGGLE);
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mdelay(125);
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}
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led_set_state(led, LEDST_ON);
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return 0;
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}
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static void sysconf_init(void)
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{
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#ifndef CONFIG_STM32MP1_TRUSTED
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u8 *syscfg;
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#ifdef CONFIG_DM_REGULATOR
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struct udevice *pwr_dev;
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struct udevice *pwr_reg;
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struct udevice *dev;
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int ret;
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u32 otp = 0;
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#endif
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u32 bootr;
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syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
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/* interconnect update : select master using the port 1 */
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/* LTDC = AXI_M9 */
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/* GPU = AXI_M8 */
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/* today information is hardcoded in U-Boot */
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writel(BIT(9), syscfg + SYSCFG_ICNR);
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/* disable Pull-Down for boot pin connected to VDD */
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bootr = readl(syscfg + SYSCFG_BOOTR);
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bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
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bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
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writel(bootr, syscfg + SYSCFG_BOOTR);
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#ifdef CONFIG_DM_REGULATOR
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/* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
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* and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
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* The customer will have to disable this for low frequencies
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* or if AFMUX is selected but the function not used, typically for
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* TRACE. Otherwise, impact on power consumption.
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*
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* WARNING:
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* enabling High Speed mode while VDD>2.7V
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* with the OTP product_below_2v5 (OTP 18, BIT 13)
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* erroneously set to 1 can damage the IC!
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* => U-Boot set the register only if VDD < 2.7V (in DT)
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* but this value need to be consistent with board design
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*/
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ret = syscon_get_by_driver_data(STM32MP_SYSCON_PWR, &pwr_dev);
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if (!ret) {
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(stm32mp_bsec),
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&dev);
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if (ret) {
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pr_err("Can't find stm32mp_bsec driver\n");
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return;
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}
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ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
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if (!ret)
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otp = otp & BIT(13);
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/* get VDD = pwr-supply */
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ret = device_get_supply_regulator(pwr_dev, "pwr-supply",
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&pwr_reg);
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/* check if VDD is Low Voltage */
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if (!ret) {
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if (regulator_get_value(pwr_reg) < 2700000) {
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writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
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SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
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SYSCFG_IOCTRLSETR_HSLVEN_ETH |
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SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
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SYSCFG_IOCTRLSETR_HSLVEN_SPI,
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syscfg + SYSCFG_IOCTRLSETR);
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if (!otp)
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pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
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} else {
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if (otp)
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pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
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}
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} else {
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debug("VDD unknown");
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}
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}
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#endif
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/* activate automatic I/O compensation
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* warning: need to ensure CSI enabled and ready in clock driver
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*/
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writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
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while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
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;
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clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
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#endif
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}
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/* board dependent setup after realloc */
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int board_init(void)
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{
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struct udevice *dev;
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/* address of boot parameters */
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gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
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/* probe all PINCTRL for hog */
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for (uclass_first_device(UCLASS_PINCTRL, &dev);
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dev;
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uclass_next_device(&dev)) {
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pr_debug("probe pincontrol = %s\n", dev->name);
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}
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board_key_check();
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sysconf_init();
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if (IS_ENABLED(CONFIG_LED))
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led_default_state();
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return 0;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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const void *fdt_compat;
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int fdt_compat_len;
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fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
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&fdt_compat_len);
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if (fdt_compat && fdt_compat_len) {
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if (strncmp(fdt_compat, "st,", 3) != 0)
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env_set("board_name", fdt_compat);
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else
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env_set("board_name", fdt_compat + 3);
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}
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#endif
|
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/* for DK1/DK2 boards */
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board_check_usb_power();
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return 0;
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}
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void board_quiesce_devices(void)
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{
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setup_led(LEDST_OFF);
|
}
|
|
/* eth init function : weak called in eqos driver */
|
int board_interface_eth_init(struct udevice *dev,
|
phy_interface_t interface_type)
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{
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u8 *syscfg;
|
u32 value;
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bool eth_clk_sel_reg = false;
|
bool eth_ref_clk_sel_reg = false;
|
|
/* Gigabit Ethernet 125MHz clock selection. */
|
eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
|
|
/* Ethernet 50Mhz RMII clock selection */
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eth_ref_clk_sel_reg =
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dev_read_bool(dev, "st,eth_ref_clk_sel");
|
|
syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
|
|
if (!syscfg)
|
return -ENODEV;
|
|
switch (interface_type) {
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case PHY_INTERFACE_MODE_MII:
|
value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
|
SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
|
debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
|
break;
|
case PHY_INTERFACE_MODE_GMII:
|
if (eth_clk_sel_reg)
|
value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
|
SYSCFG_PMCSETR_ETH_CLK_SEL;
|
else
|
value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
|
debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
|
break;
|
case PHY_INTERFACE_MODE_RMII:
|
if (eth_ref_clk_sel_reg)
|
value = SYSCFG_PMCSETR_ETH_SEL_RMII |
|
SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
|
else
|
value = SYSCFG_PMCSETR_ETH_SEL_RMII;
|
debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
|
break;
|
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
if (eth_clk_sel_reg)
|
value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
|
SYSCFG_PMCSETR_ETH_CLK_SEL;
|
else
|
value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
|
debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
|
break;
|
default:
|
debug("%s: Do not manage %d interface\n",
|
__func__, interface_type);
|
/* Do not manage others interfaces */
|
return -EINVAL;
|
}
|
|
/* clear and set ETH configuration bits */
|
writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
|
SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
|
syscfg + SYSCFG_PMCCLRR);
|
writel(value, syscfg + SYSCFG_PMCSETR);
|
|
return 0;
|
}
|
