/*
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* Copyright (C) 2012 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spartan3.h>
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#include <command.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_misc.h>
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#include <asm/arch/spr_ssp.h>
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/*
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* FPGA program pin configuration on X600:
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*
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* Only PROG and DONE are connected to GPIOs. INIT is not connected to the
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* SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
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* 16bit serial writes via this SSP port to write the data bits into the
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* FPGA.
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*/
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#define CONFIG_SYS_FPGA_PROG 2
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#define CONFIG_SYS_FPGA_DONE 3
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/*
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* Set the active-low FPGA reset signal.
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*/
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static void fpga_reset(int assert)
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{
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/*
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* On x600 we have no means to toggle the FPGA reset signal
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*/
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debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
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}
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/*
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* Set the FPGA's active-low SelectMap program line to the specified level
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*/
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static int fpga_pgm_fn(int assert, int flush, int cookie)
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{
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debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
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gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
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return assert;
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}
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/*
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* Test the state of the active-low FPGA INIT line. Return 1 on INIT
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* asserted (low).
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*/
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static int fpga_init_fn(int cookie)
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{
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static int state;
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debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
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/*
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* On x600, the FPGA INIT signal is not connected to the SoC.
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* We can't read the INIT status. Let's return the "correct"
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* INIT signal state generated via a local state-machine.
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*/
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if (++state == 1) {
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return 1;
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} else {
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state = 0;
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return 0;
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}
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}
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/*
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* Test the state of the active-high FPGA DONE pin
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*/
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static int fpga_done_fn(int cookie)
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{
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struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
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/*
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* Wait for Tx-FIFO to become empty before looking for DONE
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*/
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while (!(readl(&ssp->sspsr) & SSPSR_TFE))
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;
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if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
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return 1;
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else
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return 0;
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}
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/*
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* FPGA pre-configuration function. Just make sure that
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* FPGA reset is asserted to keep the FPGA from starting up after
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* configuration.
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*/
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static int fpga_pre_config_fn(int cookie)
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{
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debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
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fpga_reset(true);
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return 0;
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}
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/*
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* FPGA post configuration function. Blip the FPGA reset line and then see if
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* the FPGA appears to be running.
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*/
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static int fpga_post_config_fn(int cookie)
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{
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int rc = 0;
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debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
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fpga_reset(true);
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udelay(100);
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fpga_reset(false);
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udelay(100);
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return rc;
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}
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static int fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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/*
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* No dedicated clock signal on x600 (data & clock generated)
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* in SSP interface. So we don't have to do anything here.
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*/
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return assert_clk;
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}
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static int fpga_wr_fn(int assert_write, int flush, int cookie)
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{
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struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
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static int count;
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static u16 data;
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/*
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* First collect 16 bits of data
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*/
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data = data << 1;
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if (assert_write)
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data |= 1;
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/*
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* If 16 bits are not available, return for more bits
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*/
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count++;
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if (count != 16)
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return assert_write;
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count = 0;
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/*
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* Wait for Tx-FIFO to become ready
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*/
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while (!(readl(&ssp->sspsr) & SSPSR_TNF))
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;
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/* Send 16 bits to FPGA via SSP bus */
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writel(data, &ssp->sspdr);
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return assert_write;
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}
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static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
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fpga_pre_config_fn,
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fpga_pgm_fn,
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fpga_clk_fn,
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fpga_init_fn,
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fpga_done_fn,
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fpga_wr_fn,
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fpga_post_config_fn,
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};
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static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
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XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
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};
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/*
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* Initialize the SelectMap interface. We assume that the mode and the
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* initial state of all of the port pins have already been set!
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*/
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static void fpga_serialslave_init(void)
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{
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debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
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fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
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}
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static int expi_setup(int freq)
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{
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struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
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pll2_m = (freq * 2) / 1000;
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pll2_n = 15;
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pll2_p = 1;
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expi_x = 1;
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expi_y = 2;
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/*
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* Disable reset, Low compression, Disable retiming, Enable Expi,
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* Enable soft reset, DMA, PLL2, Internal
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*/
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writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
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EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
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EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
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&misc->expi_clk_cfg);
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/*
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* 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
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* Enable PLL2, Disable reset
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*/
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writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
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writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
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PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
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/*
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* Disable soft reset
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*/
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clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
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return 0;
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}
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/*
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* Initialize the fpga
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*/
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int x600_init_fpga(void)
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{
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struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
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struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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/* Enable SSP2 clock */
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writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
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&misc->periph1_clken);
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/* Set EXPI clock to 45 MHz */
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expi_setup(45000);
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/* Configure GPIO directions */
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gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
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gpio_direction_input(CONFIG_SYS_FPGA_DONE);
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writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
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writel(SSPCR1_SSE, &ssp->sspcr1);
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/*
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* Set lowest prescale divisor value (CPSDVSR) of 2 for max download
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* speed.
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*
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* Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
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* With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
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*/
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writel(2, &ssp->sspcpsr);
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fpga_init();
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fpga_serialslave_init();
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debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
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fpga_add(fpga_xilinx, &fpga[0]);
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return 0;
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}
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