/*
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* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
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* Copyright 2007 Embedded Specialties, Inc.
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* Joe Hamman joe.hamman@embeddedspecialties.com
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*
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* Copyright 2004 Freescale Semiconductor.
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_86xx.h>
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#include <asm/fsl_pci.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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long int fixed_sdram (void);
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int board_early_init_f (void)
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{
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return 0;
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}
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int checkboard (void)
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{
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puts ("Board: Wind River SBC8641D\n");
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return 0;
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}
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int dram_init(void)
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{
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long dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fixed_sdram ();
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#endif
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debug (" DDR: ");
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gd->ram_size = dram_size;
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return 0;
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}
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#if defined(CONFIG_SYS_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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puts ("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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puts ("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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puts ("SDRAM test passed.\n");
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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long int fixed_sdram (void)
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{
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#if !defined(CONFIG_SYS_RAMBOOT)
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
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ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
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ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
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ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
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ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
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ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
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ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
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ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
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asm ("sync;isync");
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udelay (500);
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ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
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asm ("sync; isync");
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udelay (500);
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ddr = &immap->im_ddr2;
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ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
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ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
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ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
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ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
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ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
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ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
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ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
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ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
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ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
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ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
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ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
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ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
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ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
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ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
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asm ("sync;isync");
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udelay (500);
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ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
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asm ("sync; isync");
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udelay (500);
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#endif
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI Devices, report devices found.
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*/
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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FT_FSL_PCI_SETUP;
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return 0;
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}
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#endif
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void sbc8641d_reset_board (void)
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{
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puts ("Resetting board....\n");
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}
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/*
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* get_board_sys_clk
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* Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
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*/
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unsigned long get_board_sys_clk (ulong dummy)
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{
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int i;
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ulong val = 0;
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i = 5;
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i &= 0x07;
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switch (i) {
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case 0:
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val = 33000000;
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break;
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case 1:
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val = 40000000;
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break;
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case 2:
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val = 50000000;
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break;
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case 3:
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val = 66000000;
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break;
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case 4:
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val = 83000000;
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break;
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case 5:
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val = 100000000;
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break;
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case 6:
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val = 134000000;
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break;
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case 7:
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val = 166000000;
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break;
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}
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return val;
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}
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void board_reset(void)
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{
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#ifdef CONFIG_SYS_RESET_ADDRESS
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ulong addr = CONFIG_SYS_RESET_ADDRESS;
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/* flush and disable I/D cache */
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__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
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__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
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__asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
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__asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("mtspr 1008, 4");
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__asm__ __volatile__ ("isync");
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("mtspr 1008, 5");
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__asm__ __volatile__ ("isync");
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__asm__ __volatile__ ("sync");
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/*
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* SRR0 has system reset vector, SRR1 has default MSR value
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* rfi restores MSR from SRR1 and sets the PC to the SRR0 value
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*/
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__asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
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__asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
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__asm__ __volatile__ ("mtspr 27, 4");
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__asm__ __volatile__ ("rfi");
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#endif
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}
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