/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x0fff_ffff DDR 256M
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCIe MEM 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe27f_ffff PCI1 IO 8M
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* 0xe280_0000 0xe2ff_ffff PCIe IO 8M
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* 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M
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* 0xf8b0_0000 0xf80f_ffff EEPROM 1M
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
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*
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* If swapped CS0/CS6 via JP12+SW2.8:
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* 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
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* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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struct law_entry law_table[] = {
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#ifdef CONFIG_SYS_ALT_BOOT
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SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
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#else
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SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
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#endif
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#ifndef CONFIG_SPD_EEPROM
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
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#endif
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#ifdef CONFIG_SYS_LBC_SDRAM_BASE
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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#else
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/* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
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SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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