/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <i2c.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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/*
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* Factors to consider for clock adjust:
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* - number of chips on bus
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* - position of slot
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* - DDR1 vs. DDR2?
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* - ???
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*
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* This needs to be determined on a board-by-board basis.
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* 0110 3/4 cycle late
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* 0111 7/8 cycle late
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*/
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popts->clk_adjust = 7;
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/*
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* Factors to consider for CPO:
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* - frequency
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* - ddr1 vs. ddr2
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*/
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popts->cpo_override = 10;
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/*
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* Factors to consider for write data delay:
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* - number of DIMMs
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*
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* 1 = 1/4 clock delay
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* 2 = 1/2 clock delay
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* 3 = 3/4 clock delay
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* 4 = 1 clock delay
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* 5 = 5/4 clock delay
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* 6 = 3/2 clock delay
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*/
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popts->write_data_delay = 3;
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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}
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#ifdef CONFIG_SPD_EEPROM
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/*
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* Workaround for hardware errata. An i2c address conflict
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* existed on earlier boards; the workaround moved the DDR
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* SPD from 0x51 to 0x53. So we try and read 0x53 1st, and
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* if that fails, then fall back to reading at 0x51.
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*/
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void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
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{
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int ret;
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#ifdef ALT_SPD_EEPROM_ADDRESS
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if (i2c_address == SPD_EEPROM_ADDRESS) {
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ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
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sizeof(generic_spd_eeprom_t));
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if (ret == 0)
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return; /* Good data at 0x53 */
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memset(spd, 0, sizeof(generic_spd_eeprom_t));
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}
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#endif
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ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
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sizeof(generic_spd_eeprom_t));
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if (ret) {
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printf("DDR: failed to read SPD from addr %u\n", i2c_address);
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memset(spd, 0, sizeof(generic_spd_eeprom_t));
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}
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}
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#else
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/*
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* fixed_sdram init -- doesn't use serial presence detect.
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* Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
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*/
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phys_size_t fixed_sdram(void)
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{
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struct ccsr_ddr __iomem *ddr =
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(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
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out_be32(&ddr->cs0_bnds, 0x0000007f);
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out_be32(&ddr->cs1_bnds, 0x008000ff);
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out_be32(&ddr->cs2_bnds, 0x00000000);
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out_be32(&ddr->cs3_bnds, 0x00000000);
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out_be32(&ddr->cs0_config, 0x80010101);
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out_be32(&ddr->cs1_config, 0x80010101);
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out_be32(&ddr->cs2_config, 0x00000000);
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out_be32(&ddr->cs3_config, 0x00000000);
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out_be32(&ddr->timing_cfg_3, 0x00000000);
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out_be32(&ddr->timing_cfg_0, 0x00220802);
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out_be32(&ddr->timing_cfg_1, 0x38377322);
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out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
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out_be32(&ddr->sdram_cfg, 0x4300C000);
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out_be32(&ddr->sdram_cfg_2, 0x24401000);
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out_be32(&ddr->sdram_mode, 0x23C00542);
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out_be32(&ddr->sdram_mode_2, 0x00000000);
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out_be32(&ddr->sdram_interval, 0x05080100);
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out_be32(&ddr->sdram_md_cntl, 0x00000000);
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out_be32(&ddr->sdram_data_init, 0x00000000);
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out_be32(&ddr->sdram_clk_cntl, 0x03800000);
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asm("sync;isync;msync");
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udelay(500);
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#ifdef CONFIG_DDR_ECC
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/* Enable ECC checking */
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
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#else
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
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#endif
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif
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