/*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmc.h>
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#include <spi.h>
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#include <spi_flash.h>
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int checkboard(void)
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{
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puts("BOARD: SH7753 EVB\n");
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return 0;
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}
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static void init_gpio(void)
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{
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struct gpio_regs *gpio = GPIO_BASE;
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struct sermux_regs *sermux = SERMUX_BASE;
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/* GPIO */
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writew(0x0000, &gpio->pacr); /* GETHER */
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writew(0x0001, &gpio->pbcr); /* INTC */
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writew(0x0000, &gpio->pccr); /* PWMU, INTC */
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writew(0x0000, &gpio->pdcr); /* SPI0 */
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writew(0xeaff, &gpio->pecr); /* GPIO */
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writew(0x0000, &gpio->pfcr); /* WDT */
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writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
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writew(0x0000, &gpio->phcr); /* SPI1 */
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writew(0x0000, &gpio->picr); /* SDHI */
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writew(0x0000, &gpio->pjcr); /* SCIF4 */
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writew(0x0003, &gpio->pkcr); /* SerMux */
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writew(0x0000, &gpio->plcr); /* SerMux */
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writew(0x0000, &gpio->pmcr); /* RIIC */
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writew(0x0000, &gpio->pncr); /* USB, SGPIO */
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writew(0x0000, &gpio->pocr); /* SGPIO */
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writew(0xd555, &gpio->pqcr); /* GPIO */
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writew(0x0000, &gpio->prcr); /* RIIC */
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writew(0x0000, &gpio->pscr); /* RIIC */
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writew(0x0000, &gpio->ptcr); /* STATUS */
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writeb(0x00, &gpio->pudr);
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writew(0x5555, &gpio->pucr); /* Debug LED */
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writew(0x0000, &gpio->pvcr); /* RSPI */
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writew(0x0000, &gpio->pwcr); /* EVC */
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writew(0x0000, &gpio->pxcr); /* LBSC */
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writew(0x0000, &gpio->pycr); /* LBSC */
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writew(0x0000, &gpio->pzcr); /* eMMC */
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writew(0xfe00, &gpio->psel0);
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writew(0x0000, &gpio->psel1);
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writew(0x3000, &gpio->psel2);
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writew(0xff00, &gpio->psel3);
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writew(0x771f, &gpio->psel4);
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writew(0x0ffc, &gpio->psel5);
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writew(0x00ff, &gpio->psel6);
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writew(0xfc00, &gpio->psel7);
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writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
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}
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static void init_usb_phy(void)
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{
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struct usb_common_regs *common0 = USB0_COMMON_BASE;
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struct usb_common_regs *common1 = USB1_COMMON_BASE;
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struct usb0_phy_regs *phy = USB0_PHY_BASE;
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struct usb1_port_regs *port = USB1_PORT_BASE;
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struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
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writew(0x0100, &phy->reset); /* set reset */
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/* port0 = USB0, port1 = USB1 */
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writew(0x0002, &phy->portsel);
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writel(0x0001, &port->port1sel); /* port1 = Host */
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writew(0x0111, &phy->reset); /* clear reset */
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writew(0x4000, &common0->suspmode);
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writew(0x4000, &common1->suspmode);
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#if defined(__LITTLE_ENDIAN)
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writel(0x00000000, &align->ehcidatac);
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writel(0x00000000, &align->ohcidatac);
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#endif
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}
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static void init_gether_mdio(void)
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{
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struct gpio_regs *gpio = GPIO_BASE;
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writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
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writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
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}
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static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
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{
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struct ether_mac_regs *ether;
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unsigned char mac[6];
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unsigned long val;
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eth_parse_enetaddr(mac_string, mac);
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if (!channel)
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ether = GETHER0_MAC_BASE;
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else
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ether = GETHER1_MAC_BASE;
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val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
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writel(val, ðer->mahr);
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val = (mac[4] << 8) | mac[5];
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writel(val, ðer->malr);
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}
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#if defined(CONFIG_SH_32BIT)
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/*****************************************************************
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* This PMB must be set on this timing. The lowlevel_init is run on
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* Area 0(phys 0x00000000), so we have to map it.
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*
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* The new PMB table is following:
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* ent virt phys v sz c wt
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* 0 0xa0000000 0x40000000 1 128M 0 1
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* 1 0xa8000000 0x48000000 1 128M 0 1
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* 2 0xb0000000 0x50000000 1 128M 0 1
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* 3 0xb8000000 0x58000000 1 128M 0 1
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* 4 0x80000000 0x40000000 1 128M 1 1
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* 5 0x88000000 0x48000000 1 128M 1 1
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* 6 0x90000000 0x50000000 1 128M 1 1
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* 7 0x98000000 0x58000000 1 128M 1 1
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*/
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static void set_pmb_on_board_init(void)
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{
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struct mmu_regs *mmu = MMU_BASE;
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/* clear ITLB */
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writel(0x00000004, &mmu->mmucr);
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/* delete PMB for SPIBOOT */
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writel(0, PMB_ADDR_BASE(0));
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writel(0, PMB_DATA_BASE(0));
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/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
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/* ppn ub v s1 s0 c wt */
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writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
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writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
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writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
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writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
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writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
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writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
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writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
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writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
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writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
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writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
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writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
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writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
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}
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#endif
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int board_init(void)
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{
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struct gether_control_regs *gether = GETHER_CONTROL_BASE;
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init_gpio();
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#if defined(CONFIG_SH_32BIT)
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set_pmb_on_board_init();
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#endif
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/* Sets TXnDLY to B'010 */
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writel(0x00000202, &gether->gbecont);
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init_usb_phy();
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init_gether_mdio();
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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struct gpio_regs *gpio = GPIO_BASE;
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writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
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writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
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udelay(1);
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writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
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udelay(200);
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return mmcif_mmc_init();
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}
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static int get_sh_eth_mac_raw(unsigned char *buf, int size)
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{
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struct spi_flash *spi;
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int ret;
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spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
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if (spi == NULL) {
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printf("%s: spi_flash probe failed.\n", __func__);
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return 1;
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}
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ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
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if (ret) {
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printf("%s: spi_flash read failed.\n", __func__);
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spi_flash_free(spi);
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return 1;
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}
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spi_flash_free(spi);
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return 0;
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}
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static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
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{
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memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
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SH7753EVB_ETHERNET_MAC_SIZE);
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mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
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return 0;
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}
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static void init_ethernet_mac(void)
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{
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char mac_string[64];
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char env_string[64];
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int i;
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unsigned char *buf;
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buf = malloc(256);
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if (!buf) {
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printf("%s: malloc failed.\n", __func__);
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return;
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}
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get_sh_eth_mac_raw(buf, 256);
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/* Gigabit Ethernet */
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for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
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get_sh_eth_mac(i, mac_string, buf);
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if (i == 0)
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env_set("ethaddr", mac_string);
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else {
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sprintf(env_string, "eth%daddr", i);
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env_set(env_string, mac_string);
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}
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set_mac_to_sh_giga_eth_register(i, mac_string);
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}
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free(buf);
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}
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int board_late_init(void)
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{
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init_ethernet_mac();
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return 0;
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}
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int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int i, ret;
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char mac_string[256];
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struct spi_flash *spi;
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unsigned char *buf;
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if (argc != 3) {
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buf = malloc(256);
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if (!buf) {
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printf("%s: malloc failed.\n", __func__);
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return 1;
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}
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get_sh_eth_mac_raw(buf, 256);
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/* print current MAC address */
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for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
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get_sh_eth_mac(i, mac_string, buf);
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printf("GETHERC ch%d = %s\n", i, mac_string);
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}
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free(buf);
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return 0;
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}
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/* new setting */
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memset(mac_string, 0xff, sizeof(mac_string));
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sprintf(mac_string, "%s\t%s",
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argv[1], argv[2]);
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/* write MAC data to SPI rom */
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spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
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if (!spi) {
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printf("%s: spi_flash probe failed.\n", __func__);
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return 1;
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}
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ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
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SH7753EVB_SPI_SECTOR_SIZE);
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if (ret) {
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printf("%s: spi_flash erase failed.\n", __func__);
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return 1;
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}
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ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
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sizeof(mac_string), mac_string);
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if (ret) {
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printf("%s: spi_flash write failed.\n", __func__);
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spi_flash_free(spi);
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return 1;
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}
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spi_flash_free(spi);
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puts("The writing of the MAC address to SPI ROM was completed.\n");
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return 0;
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}
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U_BOOT_CMD(
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write_mac, 3, 1, do_write_mac,
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"write MAC address for GETHERC",
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"[GETHERC ch0] [GETHERC ch1]\n"
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);
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