/*
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* Maintainer : Steve Sakoman <steve@sakoman.com>
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*
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* Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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*
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include "overo.h"
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on both banks.
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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timings->mr = MICRON_V_MR_165;
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switch (get_board_revision()) {
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case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
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timings->mcfg = MICRON_V_MCFG_165(256 << 20);
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timings->ctrla = MICRON_V_ACTIMA_165;
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timings->ctrlb = MICRON_V_ACTIMB_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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break;
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case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
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case REVISION_4:
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timings->mcfg = MICRON_V_MCFG_200(256 << 20);
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timings->ctrla = MICRON_V_ACTIMA_200;
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timings->ctrlb = MICRON_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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break;
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case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
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timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
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timings->ctrla = HYNIX_V_ACTIMA_200;
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timings->ctrlb = HYNIX_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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break;
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case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
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timings->mcfg = MCFG(512 << 20, 15);
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timings->ctrla = MICRON_V_ACTIMA_200;
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timings->ctrlb = MICRON_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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break;
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default:
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timings->mcfg = MICRON_V_MCFG_165(128 << 20);
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timings->ctrla = MICRON_V_ACTIMA_165;
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timings->ctrlb = MICRON_V_ACTIMB_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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}
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}
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