/*
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* Novena video output support
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*
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* IT6251 code based on code Copyright (C) 2014 Sean Cross
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* from https://github.com/xobs/novena-linux.git commit
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* 3d85836ee1377d445531928361809612aa0a18db
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*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/video.h>
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#include <i2c.h>
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#include <input.h>
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#include <ipu_pixfmt.h>
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#include <linux/fb.h>
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#include <linux/input.h>
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#include <malloc.h>
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#include <stdio_dev.h>
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#include "novena.h"
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#define IT6251_VENDOR_ID_LOW 0x00
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#define IT6251_VENDOR_ID_HIGH 0x01
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#define IT6251_DEVICE_ID_LOW 0x02
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#define IT6251_DEVICE_ID_HIGH 0x03
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#define IT6251_SYSTEM_STATUS 0x0d
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#define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0)
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#define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1)
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#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2)
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#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3)
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#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4)
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#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5)
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#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6)
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#define IT6251_REF_STATE 0x0e
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#define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0)
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#define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1)
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#define IT6251_REF_STATE_CR_PATTERN (1 << 2)
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#define IT6251_REF_STATE_EQ_PATTERN (1 << 3)
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#define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4)
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#define IT6251_REF_STATE_MUTED (1 << 5)
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#define IT6251_REG_PCLK_CNT_LOW 0x57
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#define IT6251_REG_PCLK_CNT_HIGH 0x58
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#define IT6521_RETRY_MAX 20
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static int it6251_is_stable(void)
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{
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const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
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const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
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int status;
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int clkcnt;
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int rpclkcnt;
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int refstate;
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rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
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((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
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debug("RPCLKCnt: %d\n", rpclkcnt);
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status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
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debug("System status: 0x%02x\n", status);
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clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
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((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
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0x0f00);
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debug("Clock: 0x%02x\n", clkcnt);
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refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
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debug("Ref Link State: 0x%02x\n", refstate);
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if ((refstate & 0x1f) != 0)
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return 0;
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/* If video is muted, that's a failure */
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if (refstate & IT6251_REF_STATE_MUTED)
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return 0;
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if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
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return 0;
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return 1;
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}
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static int it6251_ready(void)
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{
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const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
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/* Test if the IT6251 came out of reset by reading ID regs. */
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if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
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return 0;
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if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
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return 0;
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if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
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return 0;
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if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
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return 0;
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return 1;
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}
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static void it6251_program_regs(void)
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{
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const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
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const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
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i2c_reg_write(caddr, 0x05, 0x00);
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mdelay(1);
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/* set LVDSRX address, and enable */
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i2c_reg_write(caddr, 0xfd, 0xbc);
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i2c_reg_write(caddr, 0xfe, 0x01);
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/*
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* LVDSRX
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*/
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/* This write always fails, because the chip goes into reset */
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/* reset LVDSRX */
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i2c_reg_write(laddr, 0x05, 0xff);
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i2c_reg_write(laddr, 0x05, 0x00);
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/* reset LVDSRX PLL */
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i2c_reg_write(laddr, 0x3b, 0x42);
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i2c_reg_write(laddr, 0x3b, 0x43);
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/* something with SSC PLL */
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i2c_reg_write(laddr, 0x3c, 0x08);
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/* don't swap links, but writing reserved registers */
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i2c_reg_write(laddr, 0x0b, 0x88);
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/* JEIDA, 8-bit depth 0x11, orig 0x42 */
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i2c_reg_write(laddr, 0x2c, 0x01);
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/* "reserved" */
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i2c_reg_write(laddr, 0x32, 0x04);
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/* "reserved" */
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i2c_reg_write(laddr, 0x35, 0xe0);
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/* "reserved" + clock delay */
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i2c_reg_write(laddr, 0x2b, 0x24);
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/* reset LVDSRX pix clock */
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i2c_reg_write(laddr, 0x05, 0x02);
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i2c_reg_write(laddr, 0x05, 0x00);
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/*
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* DPTX
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*/
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/* set for two lane mode, normal op, no swapping, no downspread */
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i2c_reg_write(caddr, 0x16, 0x02);
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/* some AUX channel EDID magic */
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i2c_reg_write(caddr, 0x23, 0x40);
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/* power down lanes 3-0 */
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i2c_reg_write(caddr, 0x5c, 0xf3);
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/* enable DP scrambling, change EQ CR phase */
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i2c_reg_write(caddr, 0x5f, 0x06);
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/* color mode RGB, pclk/2 */
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i2c_reg_write(caddr, 0x60, 0x02);
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/* dual pixel input mode, no EO swap, no RGB swap */
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i2c_reg_write(caddr, 0x61, 0x04);
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/* M444B24 video format */
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i2c_reg_write(caddr, 0x62, 0x01);
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/* vesa range / not interlace / vsync high / hsync high */
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i2c_reg_write(caddr, 0xa0, 0x0F);
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/* hpd event timer set to 1.6-ish ms */
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i2c_reg_write(caddr, 0xc9, 0xf5);
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/* more reserved magic */
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i2c_reg_write(caddr, 0xca, 0x4d);
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i2c_reg_write(caddr, 0xcb, 0x37);
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/* enhanced framing mode, auto video fifo reset, video mute disable */
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i2c_reg_write(caddr, 0xd3, 0x03);
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/* "vidstmp" and some reserved stuff */
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i2c_reg_write(caddr, 0xd4, 0x45);
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/* queue number -- reserved */
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i2c_reg_write(caddr, 0xe7, 0xa0);
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/* info frame packets and reserved */
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i2c_reg_write(caddr, 0xe8, 0x33);
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/* more AVI stuff */
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i2c_reg_write(caddr, 0xec, 0x00);
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/* select PC master reg for aux channel? */
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i2c_reg_write(caddr, 0x23, 0x42);
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/* send PC request commands */
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i2c_reg_write(caddr, 0x24, 0x00);
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i2c_reg_write(caddr, 0x25, 0x00);
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i2c_reg_write(caddr, 0x26, 0x00);
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/* native aux read */
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i2c_reg_write(caddr, 0x2b, 0x00);
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/* back to internal */
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i2c_reg_write(caddr, 0x23, 0x40);
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/* voltage swing level 3 */
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i2c_reg_write(caddr, 0x19, 0xff);
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/* pre-emphasis level 3 */
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i2c_reg_write(caddr, 0x1a, 0xff);
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/* start link training */
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i2c_reg_write(caddr, 0x17, 0x01);
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}
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static int it6251_init(void)
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{
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const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
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int reg;
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int tries, retries = 0;
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for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
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/* Program the chip. */
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it6251_program_regs();
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/* Wait for video stable. */
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for (tries = 0; tries < 100; tries++) {
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reg = i2c_reg_read(caddr, 0x17);
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/* Test Link CFG, STS, LCS read done. */
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if ((reg & 0xe0) != 0xe0) {
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/* Not yet, wait a bit more. */
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mdelay(2);
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continue;
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}
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/* Test if the video input is stable. */
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if (it6251_is_stable())
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return 0;
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}
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/*
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* If we couldn't stabilize, requeue and try again,
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* because it means that the LVDS channel isn't
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* stable yet.
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*/
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printf("Display didn't stabilize.\n");
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printf("This may be because the LVDS port is still in powersave mode.\n");
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mdelay(50);
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}
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return -EINVAL;
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}
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static void enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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static int lvds_enabled;
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static void enable_lvds(struct display_info_t const *dev)
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{
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if (lvds_enabled)
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return;
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/* ITE IT6251 power enable. */
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gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
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mdelay(10);
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gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
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mdelay(20);
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lvds_enabled = 1;
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}
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static int detect_lvds(struct display_info_t const *dev)
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{
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int ret, loops = 250;
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enable_lvds(dev);
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ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
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if (ret) {
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puts("Cannot select IT6251 I2C bus.\n");
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return 0;
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}
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/* Wait up-to ~250 mS for the LVDS to come up. */
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while (--loops) {
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ret = it6251_ready();
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if (ret)
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return ret;
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mdelay(1);
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}
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return 0;
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}
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struct display_info_t const displays[] = {
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{
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/* HDMI Output */
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = enable_hdmi,
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.mode = {
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.name = "HDMI",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15384,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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},
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}, {
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/* LVDS Output: N133HSE-EA1 Rev. C1 */
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.bus = -1,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_lvds,
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.enable = enable_lvds,
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.mode = {
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.name = "Chimei-FHD",
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.refresh = 60,
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.xres = 1920,
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.yres = 1080,
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.pixclock = 15384,
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.left_margin = 148,
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.right_margin = 88,
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.upper_margin = 36,
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.lower_margin = 4,
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.hsync_len = 44,
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.vsync_len = 5,
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.sync = FB_SYNC_HOR_HIGH_ACT |
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FB_SYNC_VERT_HIGH_ACT |
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FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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},
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};
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size_t display_count = ARRAY_SIZE(displays);
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static void enable_vpll(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int timeout = 100000;
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setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
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clrsetbits_le32(&ccm->analog_pll_video,
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BM_ANADIG_PLL_VIDEO_DIV_SELECT |
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BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
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BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
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BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
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writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
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writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
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clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
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while (timeout--)
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if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
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break;
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if (timeout < 0)
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printf("Warning: video pll lock timeout!\n");
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clrsetbits_le32(&ccm->analog_pll_video,
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BM_ANADIG_PLL_VIDEO_BYPASS,
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BM_ANADIG_PLL_VIDEO_ENABLE);
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}
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void setup_display_clock(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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enable_ipu_clock();
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enable_vpll();
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imx_setup_hdmi();
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/* Turn on IPU LDB DI0 clocks */
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setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
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/* Switch LDB DI0 to PLL5 (Video PLL) */
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clrsetbits_le32(&mxc_ccm->cs2cdr,
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MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
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(0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
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/* LDB clock div by 3.5 */
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clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
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/* DI0 clock derived from ldb_di0_clk */
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clrsetbits_le32(&mxc_ccm->chsccdr,
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
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(CHSCCDR_CLK_SEL_LDB_DI0 <<
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
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);
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/* Enable both LVDS channels, both connected to DI0. */
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writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
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IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
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IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
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IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
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IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
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IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
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IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
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IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
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&iomux->gpr[2]);
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clrsetbits_le32(&iomux->gpr[3],
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IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
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IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
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(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
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IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
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(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
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IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
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);
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}
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void setup_display_lvds(void)
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{
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int ret;
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ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
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if (ret) {
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puts("Cannot select LVDS-to-eDP I2C bus.\n");
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return;
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}
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/* The IT6251 should be ready now, if it's not, it's not connected. */
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ret = it6251_ready();
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if (!ret)
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return;
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/* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
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ret = it6251_init();
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if (!ret) {
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/* Backlight power enable. */
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gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
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/* PWM backlight pin, always on for full brightness. */
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gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
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}
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}
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