/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Prafulla Wadaskar <prafulla@marvell.com>
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*
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* (C) Copyright 2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <nand.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include "../common/common.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* BOCO FPGA definitions
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*/
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#define BOCO 0x10
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#define REG_CTRL_H 0x02
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#define MASK_WRL_UNITRUN 0x01
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#define MASK_RBX_PGY_PRESENT 0x40
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#define REG_IRQ_CIRQ2 0x2d
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#define MASK_RBI_DEFECT_16 0x01
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/*
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* PHY registers definitions
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*/
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#define PHY_MARVELL_OUI 0x5043
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#define PHY_MARVELL_88E1118_MODEL 0x0022
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#define PHY_MARVELL_88E1118R_MODEL 0x0024
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#define PHY_MARVELL_PAGE_REG 0x0016
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#define PHY_MARVELL_DEFAULT_PAGE 0x0000
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#define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003
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#define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
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#define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000
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#define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0)
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#define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4)
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#define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8)
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/* I/O pin to erase flash RGPP09 = MPP43 */
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#define KM_FLASH_ERASE_ENABLE 43
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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#if defined(KM_PCIE_RESET_MPP7)
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MPP7_GPO,
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#else
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MPP7_PEX_RST_OUTn,
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#endif
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#if defined(CONFIG_SYS_I2C_SOFT)
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MPP8_GPIO, /* SDA */
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MPP9_GPIO, /* SCL */
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#endif
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_GPO, /* Reserved */
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MPP13_UART1_TXD,
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MPP14_UART1_RXD,
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MPP15_GPIO, /* Not used */
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MPP16_GPIO, /* Not used */
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MPP17_GPIO, /* Reserved */
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GPIO,
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MPP21_GPIO,
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MPP22_GPIO,
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MPP23_GPIO,
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MPP24_GPIO,
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_GPIO,
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO, /* CDL1 (input) */
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MPP35_GPIO, /* CDL2 (input) */
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MPP36_GPIO, /* MAIN_IRQ (input) */
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MPP37_GPIO, /* BOARD_LED */
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MPP38_GPIO, /* Piggy3 LED[1] */
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MPP39_GPIO, /* Piggy3 LED[2] */
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MPP40_GPIO, /* Piggy3 LED[3] */
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MPP41_GPIO, /* Piggy3 LED[4] */
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MPP42_GPIO, /* Piggy3 LED[5] */
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MPP43_GPIO, /* Piggy3 LED[6] */
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MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
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MPP45_GPIO, /* Piggy3 LED[8] */
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MPP46_GPIO, /* Reserved */
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MPP47_GPIO, /* Reserved */
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MPP48_GPIO, /* Reserved */
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MPP49_GPIO, /* SW_INTOUTn */
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0
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};
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static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
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#if defined(CONFIG_KM_MGCOGE3UN)
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/*
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* Wait for startup OK from mgcoge3ne
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*/
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static int startup_allowed(void)
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{
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unsigned char buf;
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/*
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* Read CIRQ16 bit (bit 0)
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*/
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if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
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printf("%s: Error reading Boco\n", __func__);
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else
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if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
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return 1;
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return 0;
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}
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#endif
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#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
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/*
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* All boards with PIGGY4 connected via a simple switch have ethernet always
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* present.
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*/
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int ethernet_present(void)
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{
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return 1;
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}
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#else
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int ethernet_present(void)
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{
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uchar buf;
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int ret = 0;
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if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
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printf("%s: Error reading Boco\n", __func__);
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return -1;
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}
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if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
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ret = 1;
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return ret;
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}
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#endif
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static int initialize_unit_leds(void)
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{
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/*
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* Init the unit LEDs per default they all are
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* ok apart from bootstat
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*/
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uchar buf;
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if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
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printf("%s: Error reading Boco\n", __func__);
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return -1;
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}
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buf |= MASK_WRL_UNITRUN;
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if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
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printf("%s: Error writing Boco\n", __func__);
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return -1;
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}
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return 0;
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}
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static void set_bootcount_addr(void)
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{
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uchar buf[32];
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unsigned int bootcountaddr;
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bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
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sprintf((char *)buf, "0x%x", bootcountaddr);
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env_set("bootcountaddr", (char *)buf);
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}
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int misc_init_r(void)
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{
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#if defined(CONFIG_KM_MGCOGE3UN)
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char *wait_for_ne;
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u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
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wait_for_ne = env_get("waitforne");
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if ((wait_for_ne != NULL) && (dip_switch == 0)) {
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if (strcmp(wait_for_ne, "true") == 0) {
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int cnt = 0;
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int abort = 0;
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puts("NE go: ");
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while (startup_allowed() == 0) {
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if (tstc()) {
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(void) getc(); /* consume input */
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abort = 1;
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break;
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}
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udelay(200000);
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cnt++;
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if (cnt == 5)
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puts("wait\b\b\b\b");
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if (cnt == 10) {
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cnt = 0;
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puts(" \b\b\b\b");
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}
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}
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if (abort == 1)
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printf("\nAbort waiting for ne\n");
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else
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puts("OK\n");
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}
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}
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#endif
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ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
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initialize_unit_leds();
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set_km_env();
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set_bootcount_addr();
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return 0;
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}
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int board_early_init_f(void)
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{
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#if defined(CONFIG_SYS_I2C_SOFT)
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u32 tmp;
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/* set the 2 bitbang i2c pins as output gpios */
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tmp = readl(MVEBU_GPIO0_BASE + 4);
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writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
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#endif
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/* adjust SDRAM size for bank 0 */
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mvebu_sdram_size_adjust(0);
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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/*
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* The KM_FLASH_GPIO_PIN switches between using a
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* NAND or a SPI FLASH. Set this pin on start
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* to NAND mode.
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*/
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kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
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kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
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#if defined(CONFIG_SYS_I2C_SOFT)
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/*
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* Reinit the GPIO for I2C Bitbang driver so that the now
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* available gpio framework is consistent. The calls to
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* direction output in are not necessary, they are already done in
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* board_early_init_f
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*/
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kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
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kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
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#endif
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#if defined(CONFIG_SYS_EEPROM_WREN)
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kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
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kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
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#endif
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#if defined(CONFIG_KM_FPGA_CONFIG)
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trigger_fpga_config();
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#endif
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return 0;
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}
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int board_late_init(void)
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{
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#if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN))
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u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
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/* if pin 1 do full erase */
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if (dip_switch != 0) {
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/* start bootloader */
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puts("DIP: Enabled\n");
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env_set("actual_bank", "0");
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}
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#endif
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#if defined(CONFIG_KM_FPGA_CONFIG)
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wait_for_fpga_config();
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fpga_reset();
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toggle_eeprom_spi_bus();
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#endif
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return 0;
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}
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int board_spi_claim_bus(struct spi_slave *slave)
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{
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kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
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return 0;
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}
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void board_spi_release_bus(struct spi_slave *slave)
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{
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kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
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}
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#if (defined(CONFIG_KM_PIGGY4_88E6061))
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#define PHY_LED_SEL_REG 0x18
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#define PHY_LED0_LINK (0x5)
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#define PHY_LED1_ACT (0x8<<4)
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#define PHY_LED2_INT (0xe<<8)
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#define PHY_SPEC_CTRL_REG 0x1c
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#define PHY_RGMII_CLK_STABLE (0x1<<10)
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#define PHY_CLSA (0x1<<1)
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/* Configure and enable MV88E3018 PHY */
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void reset_phy(void)
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{
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char *name = "egiga0";
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unsigned short reg;
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if (miiphy_set_current_dev(name))
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return;
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/* RGMII clk transition on data stable */
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if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
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printf("Error reading PHY spec ctrl reg\n");
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if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
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reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
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printf("Error writing PHY spec ctrl reg\n");
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/* leds setup */
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if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
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PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
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printf("Error writing PHY LED reg\n");
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/* reset the phy */
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miiphy_reset(name, CONFIG_PHY_BASE_ADR);
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}
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#elif defined(CONFIG_KM_PIGGY4_88E6352)
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#include <mv88e6352.h>
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#if defined(CONFIG_KM_NUSA)
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struct mv88e_sw_reg extsw_conf[] = {
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/*
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* port 0, PIGGY4, autoneg
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* first the fix for the 1000Mbits Autoneg, this is from
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* a Marvell errata, the regs are undocumented
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*/
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{ PHY(0), PHY_PAGE, AN1000FIX_PAGE },
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{ PHY(0), PHY_STATUS, AN1000FIX },
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{ PHY(0), PHY_PAGE, 0 },
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/* now the real port and phy configuration */
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{ PORT(0), PORT_PHY, NO_SPEED_FOR },
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{ PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
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{ PHY(0), PHY_1000_CTRL, NO_ADV },
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{ PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
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{ PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
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FULL_DUPLEX },
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/* port 1, unused */
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{ PORT(1), PORT_CTRL, PORT_DIS },
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{ PHY(1), PHY_CTRL, PHY_PWR_DOWN },
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{ PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
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/* port 2, unused */
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{ PORT(2), PORT_CTRL, PORT_DIS },
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{ PHY(2), PHY_CTRL, PHY_PWR_DOWN },
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{ PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
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/* port 3, unused */
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{ PORT(3), PORT_CTRL, PORT_DIS },
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{ PHY(3), PHY_CTRL, PHY_PWR_DOWN },
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{ PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
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/* port 4, ICNEV, SerDes, SGMII */
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{ PORT(4), PORT_STATUS, NO_PHY_DETECT },
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{ PORT(4), PORT_PHY, SPEED_1000_FOR },
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{ PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
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{ PHY(4), PHY_CTRL, PHY_PWR_DOWN },
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{ PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
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/* port 5, CPU_RGMII */
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{ PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
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FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
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FULL_DPX_FOR | SPEED_1000_FOR },
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{ PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
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/* port 6, unused, this port has no phy */
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{ PORT(6), PORT_CTRL, PORT_DIS },
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};
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#else
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struct mv88e_sw_reg extsw_conf[] = {};
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#endif
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void reset_phy(void)
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{
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#if defined(CONFIG_KM_MVEXTSW_ADDR)
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char *name = "egiga0";
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if (miiphy_set_current_dev(name))
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return;
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mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
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ARRAY_SIZE(extsw_conf));
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mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
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#endif
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}
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#else
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/* Configure and enable MV88E1118 PHY on the piggy*/
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void reset_phy(void)
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{
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unsigned int oui;
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unsigned char model, rev;
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char *name = "egiga0";
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if (miiphy_set_current_dev(name))
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return;
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/* reset the phy */
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miiphy_reset(name, CONFIG_PHY_BASE_ADR);
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/* get PHY model */
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if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
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return;
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/* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
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if ((oui == PHY_MARVELL_OUI) &&
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(model == PHY_MARVELL_88E1118R_MODEL)) {
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/* set page register to 3 */
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if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
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PHY_MARVELL_PAGE_REG,
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PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
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printf("Error writing PHY page reg\n");
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/*
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* leds setup as printed on PCB:
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* LED2 (Link): 0x0 (On Link, Off No Link)
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* LED1 (Activity): 0x3 (On Activity, Off No Activity)
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* LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
|
*/
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if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
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PHY_MARVELL_88E1118R_LED_CTRL_REG,
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PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
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PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
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PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
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PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
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printf("Error writing PHY LED reg\n");
|
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/* set page register back to 0 */
|
if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
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PHY_MARVELL_PAGE_REG,
|
PHY_MARVELL_DEFAULT_PAGE))
|
printf("Error writing PHY page reg\n");
|
}
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}
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#endif
|
|
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#if defined(CONFIG_HUSH_INIT_VAR)
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int hush_init_var(void)
|
{
|
ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
|
return 0;
|
}
|
#endif
|
|
#if defined(CONFIG_SYS_I2C_SOFT)
|
void set_sda(int state)
|
{
|
I2C_ACTIVE;
|
I2C_SDA(state);
|
}
|
|
void set_scl(int state)
|
{
|
I2C_SCL(state);
|
}
|
|
int get_sda(void)
|
{
|
I2C_TRISTATE;
|
return I2C_READ;
|
}
|
|
int get_scl(void)
|
{
|
return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
|
}
|
#endif
|
|
#if defined(CONFIG_POST)
|
|
#define KM_POST_EN_L 44
|
#define POST_WORD_OFF 8
|
|
int post_hotkeys_pressed(void)
|
{
|
#if defined(CONFIG_KM_COGE5UN)
|
return kw_gpio_get_value(KM_POST_EN_L);
|
#else
|
return !kw_gpio_get_value(KM_POST_EN_L);
|
#endif
|
}
|
|
ulong post_word_load(void)
|
{
|
void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
|
return in_le32(addr);
|
|
}
|
void post_word_store(ulong value)
|
{
|
void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
|
out_le32(addr, value);
|
}
|
|
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
|
{
|
*vstart = CONFIG_SYS_SDRAM_BASE;
|
|
/* we go up to relocation plus a 1 MB margin */
|
*size = CONFIG_SYS_TEXT_BASE - (1<<20);
|
|
return 0;
|
}
|
#endif
|
|
#if defined(CONFIG_SYS_EEPROM_WREN)
|
int eeprom_write_enable(unsigned dev_addr, int state)
|
{
|
kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
|
|
return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
|
}
|
#endif
|
