/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <jffs2/load_kernel.h>
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#include <linux/mtd/rawnand.h>
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#include "igep00x0.h"
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on both banks.
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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int mfr, id, err = identify_nand_chip(&mfr, &id);
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timings->mr = MICRON_V_MR_165;
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if (!err) {
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switch (mfr) {
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case NAND_MFR_HYNIX:
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timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
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timings->ctrla = HYNIX_V_ACTIMA_200;
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timings->ctrlb = HYNIX_V_ACTIMB_200;
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break;
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case NAND_MFR_MICRON:
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timings->mcfg = MICRON_V_MCFG_200(256 << 20);
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timings->ctrla = MICRON_V_ACTIMA_200;
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timings->ctrlb = MICRON_V_ACTIMB_200;
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break;
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default:
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/* Should not happen... */
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break;
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}
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
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} else {
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if (get_cpu_family() == CPU_OMAP34XX) {
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timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
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timings->ctrla = NUMONYX_V_ACTIMA_165;
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timings->ctrlb = NUMONYX_V_ACTIMB_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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} else {
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timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
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timings->ctrla = NUMONYX_V_ACTIMA_200;
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timings->ctrlb = NUMONYX_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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}
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gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
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}
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}
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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return 0;
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}
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#endif
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