/*
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* Altera SoCFPGA SDRAM configuration
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SOCFPGA_SDRAM_CONFIG_H__
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#define __SOCFPGA_SDRAM_CONFIG_H__
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/* SDRAM configuration */
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 1
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 16
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 64
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
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#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
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#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
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#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
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#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
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#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
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#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
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#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
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#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
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#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
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#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
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/* Sequencer auto configuration */
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#define RW_MGR_ACTIVATE_0_AND_1 0x0D
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#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
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#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
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#define RW_MGR_ACTIVATE_1 0x0F
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#define RW_MGR_CLEAR_DQS_ENABLE 0x49
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#define RW_MGR_GUARANTEED_READ 0x4C
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#define RW_MGR_GUARANTEED_READ_CONT 0x54
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#define RW_MGR_GUARANTEED_WRITE 0x18
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#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
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#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
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#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
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#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
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#define RW_MGR_IDLE 0x00
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#define RW_MGR_IDLE_LOOP1 0x7B
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#define RW_MGR_IDLE_LOOP2 0x7A
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#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
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#define RW_MGR_INIT_RESET_1_CKE_0 0x74
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#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
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#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
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#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
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#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
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#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
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#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
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#define RW_MGR_MRS0_DLL_RESET 0x02
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#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
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#define RW_MGR_MRS0_USER 0x07
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#define RW_MGR_MRS0_USER_MIRR 0x0C
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#define RW_MGR_MRS1 0x03
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#define RW_MGR_MRS1_MIRR 0x09
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#define RW_MGR_MRS2 0x04
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#define RW_MGR_MRS2_MIRR 0x0A
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#define RW_MGR_MRS3 0x05
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#define RW_MGR_MRS3_MIRR 0x0B
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#define RW_MGR_PRECHARGE_ALL 0x12
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#define RW_MGR_READ_B2B 0x59
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#define RW_MGR_READ_B2B_WAIT1 0x61
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#define RW_MGR_READ_B2B_WAIT2 0x6B
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#define RW_MGR_REFRESH_ALL 0x14
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#define RW_MGR_RETURN 0x01
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#define RW_MGR_SGLE_READ 0x7D
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#define RW_MGR_ZQCL 0x06
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/* Sequencer defines configuration */
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#define AFI_RATE_RATIO 1
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#define CALIB_LFIFO_OFFSET 8
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#define CALIB_VFIFO_OFFSET 6
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#define ENABLE_SUPER_QUICK_CALIBRATION 0
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#define IO_DELAY_PER_DCHAIN_TAP 25
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#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
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#define IO_DELAY_PER_OPA_TAP 312
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#define IO_DLL_CHAIN_LENGTH 8
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#define IO_DQDQS_OUT_PHASE_MAX 0
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#define IO_DQS_EN_DELAY_MAX 31
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#define IO_DQS_EN_DELAY_OFFSET 0
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#define IO_DQS_EN_PHASE_MAX 7
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#define IO_DQS_IN_DELAY_MAX 31
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#define IO_DQS_IN_RESERVE 4
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#define IO_DQS_OUT_RESERVE 4
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#define IO_IO_IN_DELAY_MAX 31
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#define IO_IO_OUT1_DELAY_MAX 31
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#define IO_IO_OUT2_DELAY_MAX 0
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#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
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#define MAX_LATENCY_COUNT_WIDTH 5
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#define READ_VALID_FIFO_SIZE 16
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#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
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#define RW_MGR_MEM_ADDRESS_MIRRORING 0
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#define RW_MGR_MEM_DATA_MASK_WIDTH 2
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#define RW_MGR_MEM_DATA_WIDTH 16
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#define RW_MGR_MEM_DQ_PER_READ_DQS 8
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#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
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#define RW_MGR_MEM_IF_READ_DQS_WIDTH 2
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#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 2
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#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
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#define RW_MGR_MEM_NUMBER_OF_RANKS 1
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#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
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#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
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#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 2
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#define TINIT_CNTR0_VAL 99
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#define TINIT_CNTR1_VAL 32
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#define TINIT_CNTR2_VAL 32
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#define TRESET_CNTR0_VAL 99
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#define TRESET_CNTR1_VAL 99
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#define TRESET_CNTR2_VAL 10
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/* Sequencer ac_rom_init configuration */
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const u32 ac_rom_init[] = {
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0x20700000,
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0x20780000,
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0x10080431,
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0x10080530,
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0x10090044,
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0x100a00c8,
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0x100b0000,
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0x10380400,
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0x10080449,
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0x100804c8,
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0x100a0024,
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0x10090130,
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0x100b0000,
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0x30780000,
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0x38780000,
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0x30780000,
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0x10680000,
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0x106b0000,
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0x10280400,
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0x10480000,
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0x1c980000,
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0x1c9b0000,
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0x1c980008,
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0x1c9b0008,
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0x38f80000,
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0x3cf80000,
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0x38780000,
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0x18180000,
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0x18980000,
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0x13580000,
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0x135b0000,
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0x13580008,
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0x135b0008,
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0x33780000,
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0x10580008,
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0x10780000
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};
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/* Sequencer inst_rom_init configuration */
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const u32 inst_rom_init[] = {
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0x80000,
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0x80680,
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0x8180,
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0x8200,
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0x8280,
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0x8300,
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0x8380,
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0x8100,
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0x8480,
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0x8500,
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0x8580,
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0x8600,
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0x8400,
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0x800,
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0x8680,
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0x880,
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0xa680,
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0x80680,
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0x900,
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0x80680,
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0x980,
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0xa680,
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0x8680,
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0x80680,
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0xb68,
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0xcce8,
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0xae8,
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0x8ce8,
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0xb88,
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0xec88,
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0xa08,
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0xac88,
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0x80680,
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0xce00,
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0xcd80,
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0xe700,
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0xc00,
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0x20ce0,
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0x20ce0,
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0x20ce0,
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0x20ce0,
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0xd00,
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0x680,
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0x680,
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0x680,
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0x680,
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0x60e80,
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0x61080,
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0x61080,
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0x61080,
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0xa680,
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0x8680,
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0x80680,
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0xce00,
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0xcd80,
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0xe700,
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0xc00,
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0x30ce0,
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0x30ce0,
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0x30ce0,
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0x30ce0,
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0xd00,
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0x680,
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0x680,
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0x680,
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0x680,
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0x70e80,
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0x71080,
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0x71080,
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0x71080,
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0xa680,
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0x8680,
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0x80680,
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0x1158,
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0x6d8,
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0x80680,
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0x1168,
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0x7e8,
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0x7e8,
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0x87e8,
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0x40fe8,
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0x410e8,
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0x410e8,
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0x410e8,
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0x1168,
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0x7e8,
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0x7e8,
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0xa7e8,
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0x80680,
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0x40e88,
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0x41088,
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0x41088,
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0x41088,
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0x40f68,
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0x410e8,
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0x410e8,
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0x410e8,
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0xa680,
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0x40fe8,
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0x410e8,
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0x410e8,
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0x410e8,
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0x41008,
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0x41088,
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0x41088,
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0x41088,
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0x1100,
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0xc680,
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0x8680,
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0xe680,
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0x80680,
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0x0,
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0x8000,
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0xa000,
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0xc000,
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0x80000,
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0x80,
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0x8080,
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0xa080,
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0xc080,
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0x80080,
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0x9180,
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0x8680,
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0xa680,
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0x80680,
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0x40f08,
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0x80680
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};
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#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
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