/*
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* (C) Copyright 2017 Linaro
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* Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dm.h>
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#include <common.h>
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#include <asm/io.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include <asm/arch/hi3798cv200.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region poplar_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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0,
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}
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};
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struct mm_region *mem_map = poplar_mem_map;
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static const struct pl01x_serial_platdata serial_platdata = {
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.base = REG_BASE_UART0,
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.type = TYPE_PL010,
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.clock = 75000000,
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};
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U_BOOT_DEVICE(poplar_serial) = {
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.name = "serial_pl01x",
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.platdata = &serial_platdata,
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};
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int checkboard(void)
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{
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puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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psci_system_reset();
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size(NULL, 0x80000000);
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return 0;
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}
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/*
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* Some linux kernel versions don't use memory before its load address, so to
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* be generic we just pretend it isn't there. In previous uboot versions we
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* carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
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* could persist in memory and be left alone by the kernel.
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*
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* That led to a problem when mapping memory in older kernels. That PSCI code
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* now lies in memory below the kernel load offset; it therefore won't be
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* touched by the kernel, and by not specially reserving it we avoid the mapping
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* problem as well.
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*
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*/
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#define KERNEL_TEXT_OFFSET 0x00080000
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
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gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
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return 0;
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}
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static void usb2_phy_config(void)
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{
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const u32 config[] = {
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/* close EOP pre-emphasis. open data pre-emphasis */
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0xa1001c,
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/* Rcomp = 150mW, increase DC level */
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0xa00607,
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/* keep Rcomp working */
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0xa10700,
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/* Icomp = 212mW, increase current drive */
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0xa00aab,
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/* EMI fix: rx_active not stay 1 when error packets received */
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0xa11140,
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/* Comp mode select */
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0xa11041,
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/* adjust eye diagram */
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0xa0098c,
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/* adjust eye diagram */
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0xa10a0a,
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};
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int i;
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for (i = 0; i < ARRAY_SIZE(config); i++) {
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writel(config[i], PERI_CTRL_USB0);
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clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
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udelay(20);
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}
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}
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static void usb2_phy_init(void)
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{
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/* reset usb2 controller bus/utmi/roothub */
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setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
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USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
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udelay(200);
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/* reset usb2 phy por/utmi */
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setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
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udelay(200);
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/* open usb2 ref clk */
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setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
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udelay(300);
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/* cancel usb2 power on reset */
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clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
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udelay(500);
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usb2_phy_config();
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/* cancel usb2 port reset, wait comp circuit stable */
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clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
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mdelay(10);
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/* open usb2 controller clk */
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setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
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USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
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USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
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udelay(200);
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/* cancel usb2 control reset */
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clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
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USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
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udelay(200);
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}
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int board_mmc_init(bd_t *bis)
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{
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int ret;
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ret = hi6220_dwmci_add_port(0, REG_BASE_MCI, 8);
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if (ret)
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printf("mmc init error (%d)\n", ret);
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return ret;
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}
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int board_init(void)
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{
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usb2_phy_init();
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return 0;
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}
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