/*
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* (C) Copyright 2013
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* Gumstix Inc. <www.gumstix.com>
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* Maintainer: Ash Charles <ash@gumstix.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include <twl6030.h>
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#include <asm/emif.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include <asm/mach-types.h>
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#include "duovero_mux_data.h"
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#define WIFI_EN 43
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#if defined(CONFIG_CMD_NET)
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#define SMSC_NRESET 45
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static void setup_net_chip(void);
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#endif
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#ifdef CONFIG_USB_EHCI_HCD
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#include <usb.h>
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#include <asm/arch/ehci.h>
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#include <asm/ehci-omap.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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const struct omap_sysinfo sysinfo = {
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"Board: duovero\n"
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};
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struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
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/**
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* @brief board_init
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*
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* @return 0
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*/
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int board_init(void)
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{
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gpmc_init();
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gd->bd->bi_arch_number = MACH_TYPE_DUOVERO;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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/**
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* @brief misc_init_r - Configure board specific configurations
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* such as power configurations, ethernet initialization as phase2 of
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* boot sequence
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*
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* @return 0
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*/
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int misc_init_r(void)
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{
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int ret = 0;
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u8 val;
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/* wifi setup: first enable 32Khz clock from 6030 pmic */
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val = 0xe1;
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ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1);
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if (ret)
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printf("Failed to enable 32Khz clock to wifi module\n");
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/* then setup WIFI_EN as an output pin and send reset pulse */
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if (!gpio_request(WIFI_EN, "")) {
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gpio_direction_output(WIFI_EN, 0);
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gpio_set_value(WIFI_EN, 1);
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udelay(1);
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gpio_set_value(WIFI_EN, 0);
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udelay(1);
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gpio_set_value(WIFI_EN, 1);
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}
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#if defined(CONFIG_CMD_NET)
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setup_net_chip();
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#endif
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return 0;
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}
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void set_muxconf_regs(void)
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{
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do_set_mux((*ctrl)->control_padconf_core_base,
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core_padconf_array_essential,
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sizeof(core_padconf_array_essential) /
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sizeof(struct pad_conf_entry));
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do_set_mux((*ctrl)->control_padconf_wkup_base,
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wkup_padconf_array_essential,
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sizeof(wkup_padconf_array_essential) /
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sizeof(struct pad_conf_entry));
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do_set_mux((*ctrl)->control_padconf_core_base,
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core_padconf_array_non_essential,
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sizeof(core_padconf_array_non_essential) /
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sizeof(struct pad_conf_entry));
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do_set_mux((*ctrl)->control_padconf_wkup_base,
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wkup_padconf_array_non_essential,
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sizeof(wkup_padconf_array_non_essential) /
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sizeof(struct pad_conf_entry));
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}
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#if defined(CONFIG_MMC)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#if !defined(CONFIG_SPL_BUILD)
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void board_mmc_power_init(void)
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{
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twl6030_power_mmc_init(0);
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}
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#endif
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#endif
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#if defined(CONFIG_CMD_NET)
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#define GPMC_SIZE_16M 0xF
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#define GPMC_BASEADDR_MASK 0x3F
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#define GPMC_CS_ENABLE 0x1
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static void enable_gpmc_net_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
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u32 base, u32 size)
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{
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writel(0, &cs->config7);
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sdelay(1000);
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/* Delay for settling */
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writel(gpmc_config[0], &cs->config1);
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writel(gpmc_config[1], &cs->config2);
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writel(gpmc_config[2], &cs->config3);
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writel(gpmc_config[3], &cs->config4);
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writel(gpmc_config[4], &cs->config5);
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writel(gpmc_config[5], &cs->config6);
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/*
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* Enable the config. size is the CS size and goes in
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* bits 11:8. We set bit 6 to enable this CS and the base
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* address goes into bits 5:0.
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*/
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writel((size << 8) | (GPMC_CS_ENABLE << 6) |
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((base >> 24) & GPMC_BASEADDR_MASK),
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&cs->config7);
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sdelay(2000);
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}
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/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
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#define NET_LAN9221_GPMC_CONFIG1 0x2a001203
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#define NET_LAN9221_GPMC_CONFIG2 0x000a0a02
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#define NET_LAN9221_GPMC_CONFIG3 0x00020200
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#define NET_LAN9221_GPMC_CONFIG4 0x0a030a03
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#define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a
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#define NET_LAN9221_GPMC_CONFIG6 0x8a070707
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#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
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/* GPMC definitions for LAN9221 chips on expansion boards */
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static const u32 gpmc_lan_config[] = {
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NET_LAN9221_GPMC_CONFIG1,
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NET_LAN9221_GPMC_CONFIG2,
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NET_LAN9221_GPMC_CONFIG3,
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NET_LAN9221_GPMC_CONFIG4,
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NET_LAN9221_GPMC_CONFIG5,
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NET_LAN9221_GPMC_CONFIG6,
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/*CONFIG7- computed as params */
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};
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/*
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* Routine: setup_net_chip
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* Description: Setting up the configuration GPMC registers specific to the
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* Ethernet hardware.
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*/
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static void setup_net_chip(void)
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{
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enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
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GPMC_SIZE_16M);
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/* Make GPIO SMSC_NRESET as output pin and send reset pulse */
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if (!gpio_request(SMSC_NRESET, "")) {
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gpio_direction_output(SMSC_NRESET, 0);
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gpio_set_value(SMSC_NRESET, 1);
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udelay(1);
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gpio_set_value(SMSC_NRESET, 0);
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udelay(1);
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gpio_set_value(SMSC_NRESET, 1);
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}
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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#ifdef CONFIG_USB_EHCI_HCD
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
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};
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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int ret;
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unsigned int utmi_clk;
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u32 auxclk, altclksrc;
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/* Now we can enable our port clocks */
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utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
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utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
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setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
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auxclk = readl(&scrm->auxclk3);
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/* Select sys_clk */
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auxclk &= ~AUXCLK_SRCSELECT_MASK;
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auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
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/* Set the divisor to 2 */
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auxclk &= ~AUXCLK_CLKDIV_MASK;
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auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
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/* Request auxilary clock #3 */
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auxclk |= AUXCLK_ENABLE_MASK;
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writel(auxclk, &scrm->auxclk3);
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altclksrc = readl(&scrm->altclksrc);
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/* Activate alternate system clock supplier */
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altclksrc &= ~ALTCLKSRC_MODE_MASK;
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altclksrc |= ALTCLKSRC_MODE_ACTIVE;
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/* enable clocks */
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altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
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writel(altclksrc, &scrm->altclksrc);
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ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
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if (ret < 0)
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return ret;
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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return omap_ehci_hcd_stop();
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}
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#endif
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/*
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* get_board_rev() - get board revision
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*/
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u32 get_board_rev(void)
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{
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return 0x20;
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}
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