/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <malloc.h>
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#include "ch7301.h"
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#include "dp501.h"
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#include <gdsys_fpga.h>
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#define ICS8N3QV01_I2C_ADDR 0x6E
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#define ICS8N3QV01_FREF 114285000
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#define ICS8N3QV01_FREF_LL 114285000LL
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#define ICS8N3QV01_F_DEFAULT_0 156250000LL
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#define ICS8N3QV01_F_DEFAULT_1 125000000LL
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#define ICS8N3QV01_F_DEFAULT_2 100000000LL
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#define ICS8N3QV01_F_DEFAULT_3 25175000LL
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#define SIL1178_MASTER_I2C_ADDRESS 0x38
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#define SIL1178_SLAVE_I2C_ADDRESS 0x39
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#define PIXCLK_640_480_60 25180000
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#define MAX_X_CHARS 53
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#define MAX_Y_CHARS 26
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#ifdef CONFIG_SYS_OSD_DH
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#define MAX_OSD_SCREEN 8
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#define OSD_DH_BASE 4
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#else
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#define MAX_OSD_SCREEN 4
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#endif
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#ifdef CONFIG_SYS_OSD_DH
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#define OSD_SET_REG(screen, fld, val) \
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do { \
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if (screen >= OSD_DH_BASE) \
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FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
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else \
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FPGA_SET_REG(screen, osd0.fld, val); \
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} while (0)
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#else
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#define OSD_SET_REG(screen, fld, val) \
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FPGA_SET_REG(screen, osd0.fld, val)
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#endif
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#ifdef CONFIG_SYS_OSD_DH
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#define OSD_GET_REG(screen, fld, val) \
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do { \
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if (screen >= OSD_DH_BASE) \
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FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
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else \
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FPGA_GET_REG(screen, osd0.fld, val); \
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} while (0)
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#else
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#define OSD_GET_REG(screen, fld, val) \
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FPGA_GET_REG(screen, osd0.fld, val)
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#endif
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unsigned int base_width;
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unsigned int base_height;
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size_t bufsize;
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u16 *buf;
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unsigned int osd_screen_mask = 0;
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#ifdef CONFIG_SYS_ICS8N3QV01_I2C
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int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
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#endif
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#ifdef CONFIG_SYS_SIL1178_I2C
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int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
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#endif
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#ifdef CONFIG_SYS_MPC92469AC
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static void mpc92469ac_calc_parameters(unsigned int fout,
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unsigned int *post_div, unsigned int *feedback_div)
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{
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unsigned int n = *post_div;
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unsigned int m = *feedback_div;
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unsigned int a;
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unsigned int b = 14745600 / 16;
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if (fout < 50169600)
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n = 8;
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else if (fout < 100339199)
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n = 4;
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else if (fout < 200678399)
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n = 2;
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else
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n = 1;
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a = fout * n + (b / 2); /* add b/2 for proper rounding */
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m = a / b;
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*post_div = n;
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*feedback_div = m;
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}
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static void mpc92469ac_set(unsigned screen, unsigned int fout)
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{
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unsigned int n;
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unsigned int m;
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unsigned int bitval = 0;
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mpc92469ac_calc_parameters(fout, &n, &m);
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switch (n) {
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case 1:
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bitval = 0x00;
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break;
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case 2:
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bitval = 0x01;
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break;
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case 4:
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bitval = 0x02;
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break;
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case 8:
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bitval = 0x03;
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break;
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}
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FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
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}
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#endif
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#ifdef CONFIG_SYS_ICS8N3QV01_I2C
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static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
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{
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unsigned long long n;
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unsigned long long mint;
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unsigned long long mfrac;
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u8 reg_a, reg_b, reg_c, reg_d, reg_f;
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unsigned long long fout_calc;
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if (index > 3)
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return 0;
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reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
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reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
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reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
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reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
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reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
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mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
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mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
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| (reg_d >> 7);
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n = reg_d & 0x7f;
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fout_calc = (mint * ICS8N3QV01_FREF_LL
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+ mfrac * ICS8N3QV01_FREF_LL / 262144LL
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+ ICS8N3QV01_FREF_LL / 524288LL
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+ n / 2)
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/ n
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* 1000000
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/ (1000000 - 100);
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return fout_calc;
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}
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static void ics8n3qv01_calc_parameters(unsigned int fout,
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unsigned int *_mint, unsigned int *_mfrac,
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unsigned int *_n)
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{
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unsigned int n;
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unsigned int foutiic;
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unsigned int fvcoiic;
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unsigned int mint;
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unsigned long long mfrac;
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n = (2215000000U + fout / 2) / fout;
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if ((n & 1) && (n > 5))
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n -= 1;
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foutiic = fout - (fout / 10000);
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fvcoiic = foutiic * n;
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mint = fvcoiic / 114285000;
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if ((mint < 17) || (mint > 63))
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printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
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mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
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/ 114285000LL;
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*_mint = mint;
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*_mfrac = mfrac;
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*_n = n;
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}
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static void ics8n3qv01_set(unsigned int fout)
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{
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unsigned int n;
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unsigned int mint;
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unsigned int mfrac;
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unsigned int fout_calc;
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unsigned long long fout_prog;
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long long off_ppm;
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u8 reg0, reg4, reg8, reg12, reg18, reg20;
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fout_calc = ics8n3qv01_get_fout_calc(1);
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off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
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/ ICS8N3QV01_F_DEFAULT_1;
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printf(" PLL is off by %lld ppm\n", off_ppm);
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fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
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/ ICS8N3QV01_F_DEFAULT_1;
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ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
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reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
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reg0 |= (mint & 0x1f) << 1;
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reg0 |= (mfrac >> 17) & 0x01;
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
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reg4 = mfrac >> 9;
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
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reg8 = mfrac >> 1;
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
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reg12 = mfrac << 7;
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reg12 |= n & 0x7f;
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
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reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
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reg18 |= 0x20;
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
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reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
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reg20 |= mint & (1 << 5);
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i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
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}
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#endif
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static int osd_write_videomem(unsigned screen, unsigned offset,
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u16 *data, size_t charcount)
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{
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unsigned int k;
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for (k = 0; k < charcount; ++k) {
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if (offset + k >= bufsize)
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return -1;
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#ifdef CONFIG_SYS_OSD_DH
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if (screen >= OSD_DH_BASE)
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FPGA_SET_REG(screen - OSD_DH_BASE,
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videomem1[offset + k], data[k]);
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else
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FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
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#else
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FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
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#endif
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}
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return charcount;
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}
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static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned screen;
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if (argc < 5) {
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cmd_usage(cmdtp);
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return 1;
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}
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for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
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unsigned x;
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unsigned y;
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unsigned charcount;
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unsigned len;
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u8 color;
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unsigned int k;
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char *text;
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int res;
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if (!(osd_screen_mask & (1 << screen)))
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continue;
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x = simple_strtoul(argv[1], NULL, 16);
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y = simple_strtoul(argv[2], NULL, 16);
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color = simple_strtoul(argv[3], NULL, 16);
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text = argv[4];
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charcount = strlen(text);
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len = (charcount > bufsize) ? bufsize : charcount;
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for (k = 0; k < len; ++k)
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buf[k] = (text[k] << 8) | color;
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res = osd_write_videomem(screen, y * base_width + x, buf, len);
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if (res < 0)
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return res;
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OSD_SET_REG(screen, control, 0x0049);
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}
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return 0;
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}
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int osd_probe(unsigned screen)
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{
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u16 version;
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u16 features;
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int old_bus = i2c_get_bus_num();
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bool pixclock_present = false;
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bool output_driver_present = false;
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OSD_GET_REG(0, version, &version);
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OSD_GET_REG(0, features, &features);
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base_width = ((features & 0x3f00) >> 8) + 1;
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base_height = (features & 0x001f) + 1;
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bufsize = base_width * base_height;
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buf = malloc(sizeof(u16) * bufsize);
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if (!buf)
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return -1;
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#ifdef CONFIG_SYS_OSD_DH
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printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
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(screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
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(screen > 3) ? 1 : 0, version/100, version%100, base_width,
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base_height);
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#else
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printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
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screen, version/100, version%100, base_width, base_height);
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#endif
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/* setup pixclock */
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#ifdef CONFIG_SYS_MPC92469AC
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pixclock_present = true;
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mpc92469ac_set(screen, PIXCLK_640_480_60);
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#endif
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#ifdef CONFIG_SYS_ICS8N3QV01_I2C
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i2c_set_bus_num(ics8n3qv01_i2c[screen]);
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if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
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ics8n3qv01_set(PIXCLK_640_480_60);
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pixclock_present = true;
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}
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#endif
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if (!pixclock_present)
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printf(" no pixelclock found\n");
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/* setup output driver */
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#ifdef CONFIG_SYS_CH7301_I2C
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if (!ch7301_probe(screen, true))
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output_driver_present = true;
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#endif
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#ifdef CONFIG_SYS_SIL1178_I2C
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i2c_set_bus_num(sil1178_i2c[screen]);
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if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
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if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) {
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/*
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* magic initialization sequence,
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* adapted from datasheet
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*/
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i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
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output_driver_present = true;
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}
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}
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#endif
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#ifdef CONFIG_SYS_DP501_I2C
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if (!dp501_probe(screen, true))
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output_driver_present = true;
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#endif
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if (!output_driver_present)
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printf(" no output driver found\n");
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OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1));
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OSD_SET_REG(screen, x_pos, 0x007f);
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OSD_SET_REG(screen, y_pos, 0x005f);
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if (pixclock_present && output_driver_present)
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osd_screen_mask |= 1 << screen;
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i2c_set_bus_num(old_bus);
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return 0;
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}
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int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned screen;
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if ((argc < 4) || (strlen(argv[3]) % 4)) {
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cmd_usage(cmdtp);
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return 1;
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}
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for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
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unsigned x;
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unsigned y;
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unsigned k;
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u16 buffer[base_width];
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char *rp;
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u16 *wp = buffer;
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unsigned count = (argc > 4) ?
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simple_strtoul(argv[4], NULL, 16) : 1;
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if (!(osd_screen_mask & (1 << screen)))
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continue;
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x = simple_strtoul(argv[1], NULL, 16);
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y = simple_strtoul(argv[2], NULL, 16);
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rp = argv[3];
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while (*rp) {
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char substr[5];
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memcpy(substr, rp, 4);
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substr[4] = 0;
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*wp = simple_strtoul(substr, NULL, 16);
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rp += 4;
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wp++;
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if (wp - buffer > base_width)
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break;
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}
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for (k = 0; k < count; ++k) {
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unsigned offset =
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y * base_width + x + k * (wp - buffer);
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osd_write_videomem(screen, offset, buffer,
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wp - buffer);
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}
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OSD_SET_REG(screen, control, 0x0049);
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}
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return 0;
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}
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int osd_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned screen;
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unsigned x;
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unsigned y;
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if (argc < 3) {
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cmd_usage(cmdtp);
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return 1;
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}
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x = simple_strtoul(argv[1], NULL, 16);
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y = simple_strtoul(argv[2], NULL, 16);
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if (!x || (x > 64) || (x > MAX_X_CHARS) ||
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!y || (y > 32) || (y > MAX_Y_CHARS)) {
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cmd_usage(cmdtp);
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return 1;
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}
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for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
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if (!(osd_screen_mask & (1 << screen)))
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continue;
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OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
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OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
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OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
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}
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return 0;
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}
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U_BOOT_CMD(
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osdw, 5, 0, osd_write,
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"write 16-bit hex encoded buffer to osd memory",
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"pos_x pos_y buffer count\n"
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);
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U_BOOT_CMD(
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osdp, 5, 0, osd_print,
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"write ASCII buffer to osd memory",
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"pos_x pos_y color text\n"
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);
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U_BOOT_CMD(
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osdsize, 3, 0, osd_size,
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"set OSD XY size in characters",
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"size_x(max. " __stringify(MAX_X_CHARS)
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") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
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);
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