/*
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* (C) Copyright 2014
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <gdsys_fpga.h>
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#include <miiphy.h>
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#include "ihs_mdio.h"
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static int ihs_mdio_idle(struct mii_dev *bus)
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{
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struct ihs_mdio_info *info = bus->priv;
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u16 val;
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unsigned int ctr = 0;
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do {
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FPGA_GET_REG(info->fpga, mdio.control, &val);
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udelay(100);
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if (ctr++ > 10)
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return -1;
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} while (!(val & (1 << 12)));
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return 0;
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}
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static int ihs_mdio_reset(struct mii_dev *bus)
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{
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ihs_mdio_idle(bus);
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return 0;
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}
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static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr,
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int regnum)
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{
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struct ihs_mdio_info *info = bus->priv;
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u16 val;
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ihs_mdio_idle(bus);
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FPGA_SET_REG(info->fpga, mdio.control,
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((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10));
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/* wait for rx data available */
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udelay(100);
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FPGA_GET_REG(info->fpga, mdio.rx_data, &val);
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return val;
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}
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static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
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int regnum, u16 value)
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{
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struct ihs_mdio_info *info = bus->priv;
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ihs_mdio_idle(bus);
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FPGA_SET_REG(info->fpga, mdio.address_data, value);
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FPGA_SET_REG(info->fpga, mdio.control,
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((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10));
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return 0;
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}
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int ihs_mdio_init(struct ihs_mdio_info *info)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate FSL MDIO bus\n");
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return -1;
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}
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bus->read = ihs_mdio_read;
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bus->write = ihs_mdio_write;
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bus->reset = ihs_mdio_reset;
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strcpy(bus->name, info->name);
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bus->priv = info;
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return mdio_register(bus);
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}
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