/*
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* (C) Copyright 2014
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <console.h>
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#include <gdsys_fpga.h>
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enum {
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STATE_TX_PACKET_BUILDING = 1<<0,
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STATE_TX_TRANSMITTING = 1<<1,
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STATE_TX_BUFFER_FULL = 1<<2,
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STATE_TX_ERR = 1<<3,
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STATE_RECEIVE_TIMEOUT = 1<<4,
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STATE_PROC_RX_STORE_TIMEOUT = 1<<5,
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STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6,
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STATE_RX_DIST_ERR = 1<<7,
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STATE_RX_LENGTH_ERR = 1<<8,
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STATE_RX_FRAME_CTR_ERR = 1<<9,
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STATE_RX_FCS_ERR = 1<<10,
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STATE_RX_PACKET_DROPPED = 1<<11,
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STATE_RX_DATA_LAST = 1<<12,
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STATE_RX_DATA_FIRST = 1<<13,
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STATE_RX_DATA_AVAILABLE = 1<<15,
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};
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enum {
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CTRL_PROC_RECEIVE_ENABLE = 1<<12,
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CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15,
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};
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enum {
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IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5,
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IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6,
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IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7,
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IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8,
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};
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struct io_generic_packet {
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u16 target_address;
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u16 source_address;
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u8 packet_type;
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u8 bc;
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u16 packet_length;
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} __attribute__((__packed__));
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unsigned long long rx_ctr;
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unsigned long long tx_ctr;
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unsigned long long err_ctr;
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static void io_check_status(unsigned int fpga, u16 status, bool silent)
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{
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u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
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STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
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STATE_RX_PACKET_DROPPED | STATE_TX_ERR;
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if (!(status & mask)) {
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FPGA_SET_REG(fpga, ep.rx_tx_status, status);
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return;
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}
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err_ctr++;
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FPGA_SET_REG(fpga, ep.rx_tx_status, status);
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if (silent)
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return;
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if (status & STATE_RX_PACKET_DROPPED)
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printf("RX_PACKET_DROPPED, status %04x\n", status);
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if (status & STATE_RX_DIST_ERR)
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printf("RX_DIST_ERR\n");
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if (status & STATE_RX_LENGTH_ERR)
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printf("RX_LENGTH_ERR\n");
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if (status & STATE_RX_FRAME_CTR_ERR)
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printf("RX_FRAME_CTR_ERR\n");
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if (status & STATE_RX_FCS_ERR)
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printf("RX_FCS_ERR\n");
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if (status & STATE_TX_ERR)
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printf("TX_ERR\n");
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}
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static void io_send(unsigned int fpga, unsigned int size)
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{
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unsigned int k;
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struct io_generic_packet packet = {
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.source_address = 1,
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.packet_type = 1,
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.packet_length = size,
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};
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u16 *p = (u16 *)&packet;
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for (k = 0; k < sizeof(packet) / 2; ++k)
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FPGA_SET_REG(fpga, ep.transmit_data, *p++);
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for (k = 0; k < (size + 1) / 2; ++k)
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FPGA_SET_REG(fpga, ep.transmit_data, k);
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FPGA_SET_REG(fpga, ep.rx_tx_control,
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CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
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tx_ctr++;
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}
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static void io_receive(unsigned int fpga)
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{
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unsigned int k = 0;
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u16 rx_tx_status;
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
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u16 rx;
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if (rx_tx_status & STATE_RX_DATA_LAST)
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rx_ctr++;
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FPGA_GET_REG(fpga, ep.receive_data, &rx);
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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++k;
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}
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}
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static void io_reflect(unsigned int fpga)
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{
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u16 buffer[128];
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unsigned int k = 0;
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unsigned int n;
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u16 rx_tx_status;
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
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FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]);
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if (rx_tx_status & STATE_RX_DATA_LAST)
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break;
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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}
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if (!k)
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return;
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for (n = 0; n < k; ++n)
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FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]);
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FPGA_SET_REG(fpga, ep.rx_tx_control,
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CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
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tx_ctr++;
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}
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/*
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* FPGA io-endpoint reflector
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*
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* Syntax:
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* ioreflect {fpga} {reportrate}
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*/
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int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned int fpga;
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unsigned int rate = 0;
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unsigned long long last_seen = 0;
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if (argc < 2)
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return CMD_RET_USAGE;
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fpga = simple_strtoul(argv[1], NULL, 10);
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/*
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* If another parameter, it is the report rate in packets.
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*/
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if (argc > 2)
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rate = simple_strtoul(argv[2], NULL, 10);
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/* enable receive path */
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FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
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/* set device address to dummy 1*/
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FPGA_SET_REG(fpga, ep.device_address, 1);
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rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
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while (1) {
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u16 top_int;
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u16 rx_tx_status;
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FPGA_GET_REG(fpga, top_interrupt, &top_int);
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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io_check_status(fpga, rx_tx_status, true);
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if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
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(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
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io_reflect(fpga);
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if (rate) {
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if (!(tx_ctr % rate) && (tx_ctr != last_seen))
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printf("refl %llu, err %llu\n", tx_ctr,
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err_ctr);
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last_seen = tx_ctr;
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}
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if (ctrlc())
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break;
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}
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return 0;
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}
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/*
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* FPGA io-endpoint looptest
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*
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* Syntax:
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* ioloop {fpga} {size} {rate}
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*/
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#define DISP_LINE_LEN 16
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int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned int fpga;
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unsigned int size;
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unsigned int rate = 0;
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if (argc < 3)
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return CMD_RET_USAGE;
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/*
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* FPGA is specified since argc > 2
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*/
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fpga = simple_strtoul(argv[1], NULL, 10);
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/*
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* packet size is specified since argc > 2
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*/
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size = simple_strtoul(argv[2], NULL, 10);
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/*
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* If another parameter, it is the test rate in packets per second.
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*/
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if (argc > 3)
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rate = simple_strtoul(argv[3], NULL, 10);
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/* enable receive path */
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FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
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/* set device address to dummy 1*/
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FPGA_SET_REG(fpga, ep.device_address, 1);
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rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
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while (1) {
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u16 top_int;
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u16 rx_tx_status;
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FPGA_GET_REG(fpga, top_interrupt, &top_int);
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
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io_check_status(fpga, rx_tx_status, false);
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if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
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io_send(fpga, size);
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if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
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io_receive(fpga);
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if (rate) {
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if (ctrlc())
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break;
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udelay(1000000 / rate);
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if (!(tx_ctr % rate))
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printf("d %lld, tx %llu, rx %llu, err %llu\n",
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tx_ctr - rx_ctr, tx_ctr, rx_ctr,
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err_ctr);
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}
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}
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return 0;
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}
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U_BOOT_CMD(
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ioloop, 4, 0, do_ioloop,
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"fpga io-endpoint looptest",
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"fpga packetsize [packets/sec]"
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);
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U_BOOT_CMD(
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ioreflect, 3, 0, do_ioreflect,
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"fpga io-endpoint reflector",
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"fpga reportrate"
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);
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