#include <common.h>
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#include <dm.h>
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#include <miiphy.h>
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#include <asm-generic/gpio.h>
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#include "ihs_phys.h"
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#include "dt_helpers.h"
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enum {
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PORTTYPE_MAIN_CAT,
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PORTTYPE_TOP_CAT,
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PORTTYPE_16C_16F,
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PORTTYPE_UNKNOWN
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};
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static struct porttype {
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bool phy_invert_in_pol;
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bool phy_invert_out_pol;
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} porttypes[] = {
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{ true, false },
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{ false, true },
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{ false, false },
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};
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static void ihs_phy_config(struct phy_device *phydev, bool qinpn, bool qoutpn)
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{
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u16 reg;
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phy_config(phydev);
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/* enable QSGMII autonegotiation with flow control */
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phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0004);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, 16);
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reg |= (3 << 6);
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phy_write(phydev, MDIO_DEVAD_NONE, 16, reg);
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/*
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* invert QSGMII Q_INP/N and Q_OUTP/N if required
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* and perform global reset
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*/
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reg = phy_read(phydev, MDIO_DEVAD_NONE, 26);
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if (qinpn)
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reg |= (1 << 13);
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if (qoutpn)
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reg |= (1 << 12);
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reg |= (1 << 15);
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phy_write(phydev, MDIO_DEVAD_NONE, 26, reg);
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/* advertise 1000BASE-T full-duplex only */
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phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, 4);
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reg &= ~0x1e0;
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phy_write(phydev, MDIO_DEVAD_NONE, 4, reg);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, 9);
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reg = (reg & ~0x300) | 0x200;
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phy_write(phydev, MDIO_DEVAD_NONE, 9, reg);
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/* copper power up */
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reg = phy_read(phydev, MDIO_DEVAD_NONE, 16);
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reg &= ~0x0004;
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phy_write(phydev, MDIO_DEVAD_NONE, 16, reg);
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}
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uint calculate_octo_phy_mask(void)
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{
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uint k;
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uint octo_phy_mask = 0;
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struct gpio_desc gpio = {};
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char gpio_name[64];
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static const char * const dev_name[] = {"pca9698@23", "pca9698@21",
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"pca9698@24", "pca9698@25",
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"pca9698@26"};
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/* mark all octo phys that should be present */
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for (k = 0; k < 5; ++k) {
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snprintf(gpio_name, 64, "cat-gpio-%u", k);
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if (request_gpio_by_name(&gpio, dev_name[k], 0x20, gpio_name))
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continue;
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/* check CAT flag */
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if (dm_gpio_get_value(&gpio))
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octo_phy_mask |= (1 << (k * 2));
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else
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/* If CAT == 0, there's no second octo phy -> skip */
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continue;
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snprintf(gpio_name, 64, "second-octo-gpio-%u", k);
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if (request_gpio_by_name(&gpio, dev_name[k], 0x27, gpio_name)) {
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/* default: second octo phy is present */
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octo_phy_mask |= (1 << (k * 2 + 1));
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continue;
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}
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if (dm_gpio_get_value(&gpio) == 0)
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octo_phy_mask |= (1 << (k * 2 + 1));
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}
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return octo_phy_mask;
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}
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int register_miiphy_bus(uint k, struct mii_dev **bus)
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{
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int retval;
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struct mii_dev *mdiodev = mdio_alloc();
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char *name = bb_miiphy_buses[k].name;
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name,
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name,
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MDIO_NAME_LEN);
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mdiodev->read = bb_miiphy_read;
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mdiodev->write = bb_miiphy_write;
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retval = mdio_register(mdiodev);
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if (retval < 0)
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return retval;
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*bus = miiphy_get_dev_by_name(name);
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return 0;
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}
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struct porttype *get_porttype(uint octo_phy_mask, uint k)
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{
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uint octo_index = k * 4;
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if (!k) {
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if (octo_phy_mask & 0x01)
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return &porttypes[PORTTYPE_MAIN_CAT];
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else if (!(octo_phy_mask & 0x03))
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return &porttypes[PORTTYPE_16C_16F];
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} else {
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if (octo_phy_mask & (1 << octo_index))
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return &porttypes[PORTTYPE_TOP_CAT];
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}
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return NULL;
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}
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int init_single_phy(struct porttype *porttype, struct mii_dev *bus,
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uint bus_idx, uint m, uint phy_idx)
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{
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struct phy_device *phydev = phy_find_by_mask(
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bus, 1 << (m * 8 + phy_idx),
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PHY_INTERFACE_MODE_MII);
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printf(" %u", bus_idx * 32 + m * 8 + phy_idx);
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if (!phydev)
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puts("!");
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else
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ihs_phy_config(phydev, porttype->phy_invert_in_pol,
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porttype->phy_invert_out_pol);
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return 0;
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}
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int init_octo_phys(uint octo_phy_mask)
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{
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uint bus_idx;
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/* there are up to four octo-phys on each mdio bus */
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for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; ++bus_idx) {
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uint m;
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uint octo_index = bus_idx * 4;
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struct mii_dev *bus = NULL;
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struct porttype *porttype = NULL;
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int ret;
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porttype = get_porttype(octo_phy_mask, bus_idx);
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if (!porttype)
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continue;
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for (m = 0; m < 4; ++m) {
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uint phy_idx;
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/**
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* Register a bus device if there is at least one phy
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* on the current bus
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*/
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if (!m && octo_phy_mask & (0xf << octo_index)) {
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ret = register_miiphy_bus(bus_idx, &bus);
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if (ret)
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return ret;
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}
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if (!(octo_phy_mask & BIT(octo_index + m)))
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continue;
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for (phy_idx = 0; phy_idx < 8; ++phy_idx)
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init_single_phy(porttype, bus, bus_idx, m,
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phy_idx);
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}
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}
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return 0;
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}
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/*
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* MII GPIO bitbang implementation
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* MDC MDIO bus
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* 13 14 PHY1-4
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* 25 45 PHY5-8
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* 46 24 PHY9-10
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*/
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struct gpio_mii {
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int index;
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struct gpio_desc mdc_gpio;
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struct gpio_desc mdio_gpio;
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int mdc_num;
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int mdio_num;
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int mdio_value;
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} gpio_mii_set[] = {
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{ 0, {}, {}, 13, 14, 1 },
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{ 1, {}, {}, 25, 45, 1 },
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{ 2, {}, {}, 46, 24, 1 },
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};
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static int mii_mdio_init(struct bb_miiphy_bus *bus)
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{
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struct gpio_mii *gpio_mii = bus->priv;
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char name[32] = {};
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struct udevice *gpio_dev1 = NULL;
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struct udevice *gpio_dev2 = NULL;
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if (uclass_get_device_by_name(UCLASS_GPIO, "gpio@18100", &gpio_dev1) ||
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uclass_get_device_by_name(UCLASS_GPIO, "gpio@18140", &gpio_dev2)) {
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printf("Could not get GPIO device.\n");
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return 1;
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}
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if (gpio_mii->mdc_num > 31) {
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gpio_mii->mdc_gpio.dev = gpio_dev2;
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gpio_mii->mdc_gpio.offset = gpio_mii->mdc_num - 32;
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} else {
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gpio_mii->mdc_gpio.dev = gpio_dev1;
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gpio_mii->mdc_gpio.offset = gpio_mii->mdc_num;
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}
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gpio_mii->mdc_gpio.flags = 0;
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snprintf(name, 32, "bb_miiphy_bus-%d-mdc", gpio_mii->index);
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dm_gpio_request(&gpio_mii->mdc_gpio, name);
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if (gpio_mii->mdio_num > 31) {
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gpio_mii->mdio_gpio.dev = gpio_dev2;
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gpio_mii->mdio_gpio.offset = gpio_mii->mdio_num - 32;
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} else {
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gpio_mii->mdio_gpio.dev = gpio_dev1;
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gpio_mii->mdio_gpio.offset = gpio_mii->mdio_num;
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}
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gpio_mii->mdio_gpio.flags = 0;
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snprintf(name, 32, "bb_miiphy_bus-%d-mdio", gpio_mii->index);
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dm_gpio_request(&gpio_mii->mdio_gpio, name);
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dm_gpio_set_dir_flags(&gpio_mii->mdc_gpio, GPIOD_IS_OUT);
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dm_gpio_set_value(&gpio_mii->mdc_gpio, 1);
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return 0;
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}
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static int mii_mdio_active(struct bb_miiphy_bus *bus)
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{
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struct gpio_mii *gpio_mii = bus->priv;
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dm_gpio_set_value(&gpio_mii->mdc_gpio, gpio_mii->mdio_value);
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return 0;
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}
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static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
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{
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struct gpio_mii *gpio_mii = bus->priv;
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dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN);
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return 0;
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}
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static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
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{
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struct gpio_mii *gpio_mii = bus->priv;
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dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_OUT);
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dm_gpio_set_value(&gpio_mii->mdio_gpio, v);
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gpio_mii->mdio_value = v;
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return 0;
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}
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static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
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{
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struct gpio_mii *gpio_mii = bus->priv;
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dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN);
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*v = (dm_gpio_get_value(&gpio_mii->mdio_gpio));
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return 0;
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}
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static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
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{
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struct gpio_mii *gpio_mii = bus->priv;
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dm_gpio_set_value(&gpio_mii->mdc_gpio, v);
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return 0;
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}
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static int mii_delay(struct bb_miiphy_bus *bus)
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{
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udelay(1);
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return 0;
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}
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struct bb_miiphy_bus bb_miiphy_buses[] = {
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{
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.name = "ihs0",
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.init = mii_mdio_init,
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.mdio_active = mii_mdio_active,
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.mdio_tristate = mii_mdio_tristate,
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.set_mdio = mii_set_mdio,
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.get_mdio = mii_get_mdio,
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.set_mdc = mii_set_mdc,
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.delay = mii_delay,
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.priv = &gpio_mii_set[0],
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},
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{
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.name = "ihs1",
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.init = mii_mdio_init,
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.mdio_active = mii_mdio_active,
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.mdio_tristate = mii_mdio_tristate,
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.set_mdio = mii_set_mdio,
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.get_mdio = mii_get_mdio,
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.set_mdc = mii_set_mdc,
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.delay = mii_delay,
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.priv = &gpio_mii_set[1],
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},
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{
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.name = "ihs2",
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.init = mii_mdio_init,
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.mdio_active = mii_mdio_active,
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.mdio_tristate = mii_mdio_tristate,
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.set_mdio = mii_set_mdio,
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.get_mdio = mii_get_mdio,
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.set_mdc = mii_set_mdc,
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.delay = mii_delay,
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.priv = &gpio_mii_set[2],
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},
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};
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int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
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