#include <common.h>
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#include <console.h> /* ctrlc */
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#include <asm/io.h>
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#include "hydra.h"
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enum {
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HWVER_100 = 0,
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HWVER_110 = 1,
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HWVER_120 = 2,
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};
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static struct pci_device_id hydra_supported[] = {
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{ 0x6d5e, 0xcdc1 },
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{}
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};
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static struct ihs_fpga *fpga;
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struct ihs_fpga *get_fpga(void)
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{
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return fpga;
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}
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void print_hydra_version(uint index)
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{
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u32 versions = readl(&fpga->versions);
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u32 fpga_version = readl(&fpga->fpga_version);
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uint hardware_version = versions & 0xf;
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printf("FPGA%u: mapped to %p\n ", index, fpga);
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switch (hardware_version) {
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case HWVER_100:
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printf("HW-Ver 1.00\n");
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break;
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case HWVER_110:
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printf("HW-Ver 1.10\n");
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break;
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case HWVER_120:
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printf("HW-Ver 1.20\n");
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break;
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default:
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printf("HW-Ver %d(not supported)\n",
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hardware_version);
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break;
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}
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printf(" FPGA V %d.%02d\n",
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fpga_version / 100, fpga_version % 100);
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}
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void hydra_initialize(void)
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{
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uint i;
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pci_dev_t devno;
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/* Find and probe all the matching PCI devices */
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for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
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u32 val;
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/* Try to enable I/O accesses and bus-mastering */
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val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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pci_write_config_dword(devno, PCI_COMMAND, val);
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/* Make sure it worked */
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pci_read_config_dword(devno, PCI_COMMAND, &val);
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if (!(val & PCI_COMMAND_MEMORY)) {
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puts("Can't enable I/O memory\n");
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continue;
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}
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if (!(val & PCI_COMMAND_MASTER)) {
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puts("Can't enable bus-mastering\n");
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continue;
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}
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/* read FPGA details */
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fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
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PCI_REGION_MEM);
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print_hydra_version(i);
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}
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}
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#define REFL_PATTERN (0xdededede)
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#define REFL_PATTERN_INV (~REFL_PATTERN)
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int do_hydrate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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uint k = 0;
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void __iomem *pcie2_base = (void __iomem *)(MVEBU_REG_PCIE_BASE +
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0x4000);
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if (!fpga)
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return -1;
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while (1) {
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u32 res;
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writel(REFL_PATTERN, &fpga->reflection_low);
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res = readl(&fpga->reflection_low);
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if (res != REFL_PATTERN_INV)
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printf("round %u: read %08x, expected %08x\n",
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k, res, REFL_PATTERN_INV);
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writel(REFL_PATTERN_INV, &fpga->reflection_low);
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res = readl(&fpga->reflection_low);
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if (res != REFL_PATTERN)
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printf("round %u: read %08x, expected %08x\n",
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k, res, REFL_PATTERN);
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res = readl(pcie2_base + 0x118) & 0x1f;
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if (res)
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printf("FrstErrPtr %u\n", res);
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res = readl(pcie2_base + 0x104);
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if (res) {
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printf("Uncorrectable Error Status 0x%08x\n", res);
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writel(res, pcie2_base + 0x104);
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}
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if (!(++k % 10000))
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printf("round %u\n", k);
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if (ctrlc())
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break;
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}
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return 0;
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}
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U_BOOT_CMD(
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hydrate, 1, 0, do_hydrate,
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"hydra reflection test",
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"hydra reflection test"
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);
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