/*
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* Copyright (C) 2015 Stefan Roese <sr@denx.de>
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* Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <miiphy.h>
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#include <tpm.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm-generic/gpio.h>
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#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
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#include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
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#include "keyprogram.h"
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#include "dt_helpers.h"
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#include "hydra.h"
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#include "ihs_phys.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define ETH_PHY_CTRL_REG 0
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#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
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#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
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#define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff
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#define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff
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#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
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#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000
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#define DB_GP_88F68XX_GPP_POL_LOW 0x0
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#define DB_GP_88F68XX_GPP_POL_MID 0x0
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/*
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* Define the DDR layout / topology here in the board file. This will
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* be used by the DDR3 init code in the SPL U-Boot version to configure
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* the DDR3 controller.
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*/
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static struct hws_topology_map ddr_topology_map = {
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1600K, /* speed_bin */
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BUS_WIDTH_16, /* memory_width */
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MEM_4G, /* mem_size */
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DDR_FREQ_533, /* frequency */
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0, 0, /* cas_l cas_wl */
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HWS_TEMP_LOW, /* temperature */
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HWS_TIM_DEFAULT} }, /* timing */
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5, /* Num Of Bus Per Interface*/
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BUS_MASK_32BIT /* Busses mask */
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};
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static struct serdes_map serdes_topology_map[] = {
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{SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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/* SATA tx polarity is inverted */
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{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
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{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
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};
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int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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{
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*serdes_map_array = serdes_topology_map;
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*count = ARRAY_SIZE(serdes_topology_map);
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return 0;
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}
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void board_pex_config(void)
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{
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#ifdef CONFIG_SPL_BUILD
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uint k;
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struct gpio_desc gpio = {};
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if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
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/* prepare FPGA reconfiguration */
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dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
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dm_gpio_set_value(&gpio, 0);
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/* give lunatic PCIe clock some time to stabilize */
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mdelay(500);
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/* start FPGA reconfiguration */
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dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
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}
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/* wait for FPGA done */
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if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
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for (k = 0; k < 20; ++k) {
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if (dm_gpio_get_value(&gpio)) {
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printf("FPGA done after %u rounds\n", k);
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break;
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}
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mdelay(100);
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}
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}
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/* disable FPGA reset */
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if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
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dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
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dm_gpio_set_value(&gpio, 1);
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}
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/* wait for FPGA ready */
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if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
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for (k = 0; k < 2; ++k) {
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if (!dm_gpio_get_value(&gpio))
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break;
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mdelay(100);
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}
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}
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#endif
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}
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struct hws_topology_map *ddr3_get_topology_map(void)
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{
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return &ddr_topology_map;
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}
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int board_early_init_f(void)
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{
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#ifdef CONFIG_SPL_BUILD
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/* Configure MPP */
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writel(0x00111111, MVEBU_MPP_BASE + 0x00);
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writel(0x40040000, MVEBU_MPP_BASE + 0x04);
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writel(0x00466444, MVEBU_MPP_BASE + 0x08);
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writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
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writel(0x44400000, MVEBU_MPP_BASE + 0x10);
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writel(0x20000334, MVEBU_MPP_BASE + 0x14);
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writel(0x40000000, MVEBU_MPP_BASE + 0x18);
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writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
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/* Set GPP Out value */
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writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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/* Set GPP Polarity */
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writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
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/* Set GPP Out Enable */
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writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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#endif
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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void init_host_phys(struct mii_dev *bus)
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{
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uint k;
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for (k = 0; k < 2; ++k) {
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struct phy_device *phydev;
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phydev = phy_find_by_mask(bus, 1 << k,
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PHY_INTERFACE_MODE_SGMII);
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if (phydev)
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phy_config(phydev);
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}
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}
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int ccdc_eth_init(void)
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{
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uint k;
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uint octo_phy_mask = 0;
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int ret;
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struct mii_dev *bus;
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/* Init SoC's phys */
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bus = miiphy_get_dev_by_name("ethernet@34000");
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if (bus)
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init_host_phys(bus);
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bus = miiphy_get_dev_by_name("ethernet@70000");
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if (bus)
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init_host_phys(bus);
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/* Init octo phys */
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octo_phy_mask = calculate_octo_phy_mask();
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printf("IHS PHYS: %08x", octo_phy_mask);
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ret = init_octo_phys(octo_phy_mask);
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if (ret)
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return ret;
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printf("\n");
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if (!get_fpga()) {
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puts("fpga was NULL\n");
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return 1;
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}
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/* reset all FPGA-QSGMII instances */
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for (k = 0; k < 80; ++k)
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writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
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udelay(100);
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for (k = 0; k < 80; ++k)
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writel(0, get_fpga()->qsgmii_port_state[k]);
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return 0;
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}
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#endif
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int board_late_init(void)
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{
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#ifndef CONFIG_SPL_BUILD
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hydra_initialize();
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#endif
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return 0;
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}
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int board_fix_fdt(void *rw_fdt_blob)
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{
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struct udevice *bus = NULL;
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uint k;
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char name[64];
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int err;
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err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
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if (err) {
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printf("Could not get I2C bus.\n");
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return err;
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}
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for (k = 0x21; k <= 0x26; k++) {
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snprintf(name, 64,
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"/soc/internal-regs/i2c@11000/pca9698@%02x", k);
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if (!dm_i2c_simple_probe(bus, k))
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fdt_disable_by_ofname(rw_fdt_blob, name);
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}
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return 0;
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}
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int last_stage_init(void)
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{
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#ifndef CONFIG_SPL_BUILD
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ccdc_eth_init();
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#endif
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if (tpm_init() || tpm_startup(TPM_ST_CLEAR) ||
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tpm_continue_self_test()) {
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return 1;
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}
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mdelay(37);
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flush_keys();
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load_and_run_keyprog();
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return 0;
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}
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