The T2080QDS is a high-performance computing evaluation, development and
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test platform supporting the T2080 QorIQ Power Architecture processor.
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T2080 SoC Overview
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------------------
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The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
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Architecture processor cores with high-performance datapath acceleration
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logic and network and peripheral bus interfaces required for networking,
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telecom/datacom, wireless infrastructure, and mil/aerospace applications.
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T2080 includes the following functions and features:
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- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
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- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
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- Hierarchical interconnect fabric
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- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration
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- 16 SerDes lanes up to 10.3125 GHz
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- 8 Ethernet interfaces, supporting combinations of the following:
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- Up to four 10 Gbps Ethernet MACs
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- Up to eight 1 Gbps Ethernet MACs
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- Up to four 2.5 Gbps Ethernet MACs
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- High-speed peripheral interfaces
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- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
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- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
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- Additional peripheral interfaces
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- Two serial ATA (SATA 2.0) controllers
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- Two high-speed USB 2.0 controllers with integrated PHY
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- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
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- Enhanced serial peripheral interface (eSPI)
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- Four I2C controllers
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- Four 2-pin UARTs or two 4-pin UARTs
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- Integrated Flash Controller supporting NAND and NOR flash
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- Three eight-channel DMA engines
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- Support for hardware virtualization and partitioning enforcement
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- QorIQ Platform's Trust Architecture 2.0
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Differences between T2080 and T2081
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-----------------------------------
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Feature T2080 T2081
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1G Ethernet numbers: 8 6
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10G Ethernet numbers: 4 2
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SerDes lanes: 16 8
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Serial RapidIO,RMan: 2 no
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SATA Controller: 2 no
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Aurora: yes no
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SoC Package: 896-pins 780-pins
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T2080QDS feature overview
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-------------------------
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Processor:
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- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
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Memory:
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- Single memory controller capable of supporting DDR3 and DDR3-LV devices
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- Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
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Ethernet interfaces:
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- Two 1Gbps RGMII on-board ports
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- Four 10Gbps XFI on-board cages
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- 1Gbps/2.5Gbps SGMII Riser card
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- 10Gbps XAUI Riser card
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Accelerator:
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- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
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SerDes:
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- 16 lanes up to 10.3125GHz
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- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
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IFC:
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- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
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eSPI:
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- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
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USB:
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- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
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PCIE:
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- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
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SATA:
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- Two SATA 2.0 ports on-board
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SRIO:
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- Two Serial RapidIO 2.0 ports up to 5 GHz
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eSDHC:
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- Supports SD/SDHC/SDXC/eMMC Card
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I2C:
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- Four I2C controllers.
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UART:
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- Dual 4-pins UART serial ports
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System Logic:
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- QIXIS-II FPGA system controll
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Debug Features:
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- Support Legacy, COP/JTAG, Aurora, Event and EVT
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XFI:
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- XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
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a on-board SFP+ cages, which to house optical module (fiber cable) or
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direct attach cable(copper), the copper cable is used to emulate
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10GBASE-KR scenario.
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So, for XFI usage, there are two scenarios, one will use fiber cable,
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another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
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introduced to indicate a XFI port will use copper cable, and U-Boot
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will fixup the dtb accordingly.
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It's used as: fsl_10gkr_copper:<10g_mac_name>
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The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
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do not have to be coexist in hwconfig. If a MAC is listed in the env
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"fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
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will be used by default.
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for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
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hwconfig, then both four XFI ports will use copper cable.
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set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
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XFI ports will use copper cable, the other two XFI ports will use fiber
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cable.
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1000BASE-KX(1G-KX):
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- T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
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runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
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in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
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Register 1 (PCCR1), and U-Boot fixup the dtb for kernel to do proper
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initialization.
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Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
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1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
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MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
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stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
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For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
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hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
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System Memory map
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----------------
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Start Address End Address Description Size
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0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
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0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
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0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
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0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
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0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
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0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
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0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
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0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
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0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
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0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
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0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
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0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
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0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
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0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
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0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
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0x0_0000_0000 0x0_ffff_ffff DDR 4GB
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128M NOR Flash memory Map
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-------------------------
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Start Address End Address Definition Max size
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0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
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0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
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0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
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0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
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0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
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0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
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0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
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0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
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0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
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0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
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0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
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0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
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0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
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0xE8000000 0xE801FFFF RCW (current bank) 128KB
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Software configurations and board settings
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------------------------------------------
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1. NOR boot:
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a. build NOR boot image
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$ make T2080QDS_config
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$ make
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b. program u-boot.bin image to NOR flash
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=> tftp 1000000 u-boot.bin
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=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
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set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
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Switching between default bank0 and alternate bank4 on NOR flash
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To change boot source to vbank4:
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by software: run command 'qixis_reset altbank' in U-Boot.
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by DIP-switch: set SW6[1:4] = '0100'
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To change boot source to vbank0:
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by software: run command 'qixis_reset' in U-Boot.
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by DIP-Switch: set SW6[1:4] = '0000'
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2. NAND Boot:
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a. build PBL image for NAND boot
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$ make T2080QDS_NAND_config
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$ make
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b. program u-boot-with-spl-pbl.bin to NAND flash
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> nand erase 0 $filesize
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=> nand write 1000000 0 $filesize
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set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
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3. SPI Boot:
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a. build PBL image for SPI boot
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$ make T2080QDS_SPIFLASH_config
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$ make
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b. program u-boot-with-spl-pbl.bin to SPI flash
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> sf probe 0
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=> sf erase 0 f0000
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=> sf write 1000000 0 $filesize
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set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
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4. SD Boot:
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a. build PBL image for SD boot
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$ make T2080QDS_SDCARD_config
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$ make
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b. program u-boot-with-spl-pbl.bin to SD/MMC card
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> mmc write 1000000 8 0x800
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=> tftp 1000000 fsl_fman_ucode_T2080_xx.bin
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=> mmc write 1000000 0x820 80
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set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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2-stage NAND/SPI/SD boot loader
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-------------------------------
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PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
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SPL further initializes DDR using SPD and environment variables
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and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
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Finally SPL transers control to U-Boot for futher booting.
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SPL has following features:
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- Executes within 256K
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- No relocation required
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Run time view of SPL framework
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-------------------------------------------------
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|Area | Address |
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-------------------------------------------------
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|SecureBoot header | 0xFFFC0000 (32KB) |
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-------------------------------------------------
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|GD, BD | 0xFFFC8000 (4KB) |
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-------------------------------------------------
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|ENV | 0xFFFC9000 (8KB) |
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-------------------------------------------------
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|HEAP | 0xFFFCB000 (50KB) |
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-------------------------------------------------
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|STACK | 0xFFFD8000 (22KB) |
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-------------------------------------------------
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|U-Boot SPL | 0xFFFD8000 (160KB) |
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-------------------------------------------------
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NAND Flash memory Map on T2080QDS
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--------------------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF U-Boot img 1MB (2 blocks)
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0x100000 0x17FFFF U-Boot env 512KB (1 block)
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0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
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Micro SD Card memory Map on T2080QDS
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----------------------------------------------------
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Block #blocks Definition Size
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0x008 2048 U-Boot img 1MB
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0x800 0016 U-Boot env 8KB
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0x820 0128 FMAN ucode 64KB
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SPI Flash memory Map on T2080QDS
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----------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF U-Boot img 1MB
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0x100000 0x101FFF U-Boot env 8KB
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0x110000 0x11FFFF FMAN ucode 64KB
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How to update the ucode of Freescale FMAN
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-----------------------------------------
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=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin
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=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
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For more details, please refer to T2080QDS User Guide and access
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website www.freescale.com and Freescale QorIQ SDK Infocenter document.
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