T1024 SoC Overview
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------------------
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The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
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combines two or one 64-bit Power Architecture e5500 core respectively with high
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performance datapath acceleration logic, and network peripheral bus interfaces
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required for networking and telecommunications. This processor can be used in
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applications such as enterprise WLAN access points, routers, switches, firewall
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and other packet processing intensive small enterprise and branch office appliances,
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and general-purpose embedded computing. Its high level of integration offers
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significant performance benefits and greatly helps to simplify board design.
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The T1024 SoC includes the following function and features:
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- two e5500 cores, each with a private 256 KB L2 cache
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- Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
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- Three levels of instructions: User, supervisor, and hypervisor
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- Independent boot and reset
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- Secure boot capability
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- 256 KB shared L3 CoreNet platform cache (CPC)
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- Interconnect CoreNet platform
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- CoreNet coherency manager supporting coherent and noncoherent transactions
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with prioritization and bandwidth allocation amongst CoreNet endpoints
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- 150 Gbps coherent read bandwidth
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- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
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- Packet parsing, classification, and distribution
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- Queue management for scheduling, packet sequencing, and congestion management
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- Cryptography Acceleration (SEC 5.x)
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- IEEE 1588 support
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- Hardware buffer management for buffer allocation and deallocation
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- MACSEC on DPAA-based Ethernet ports
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- Ethernet interfaces
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- Four 1 Gbps Ethernet controllers
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- Parallel Ethernet interfaces
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- Two RGMII interfaces
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- High speed peripheral interfaces
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- Three PCI Express 2.0 controllers/ports running at up to 5 GHz
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- One SATA controller supporting 1.5 and 3.0 Gb/s operation
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- One QSGMII interface
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- Four SGMII interface supporting 1000 Mbps
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- Three SGMII interfaces supporting up to 2500 Mbps
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- 10GbE XFI or 10Base-KR interface
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- Additional peripheral interfaces
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- Two USB 2.0 controllers with integrated PHY
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- SD/eSDHC/eMMC
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- eSPI controller
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- Four I2C controllers
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- Four UARTs
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- Four GPIO controllers
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- Integrated flash controller (IFC)
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- LCD interface (DIU) with 12 bit dual data rate
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- Multicore programmable interrupt controller (PIC)
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- Two 8-channel DMA engines
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- Single source clocking implementation
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- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
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- QUICC Engine block
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- 32-bit RISC controller for flexible support of the communications peripherals
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- Serial DMA channel for receive and transmit on all serial channels
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- Two universal communication controllers, supporting TDM, HDLC, and UART
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T1023 Personality
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------------------
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T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
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unavailable deep sleep. Rest of the blocks are almost same as T1024.
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Differences between T1024 and T1023
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Feature T1024 T1023
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QUICC Engine: yes no
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DIU: yes no
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Deep Sleep: yes no
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I2C controller: 4 3
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DDR: 64-bit 32-bit
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IFC: 32-bit 28-bit
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Package: 23x23 19x19
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T1024RDB board Overview
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-----------------------
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- Ethernet
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- Two on-board 10M/100M/1G bps RGMII ethernet ports
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- One on-board 10G bps Base-T port.
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- DDR Memory
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- Supports 64-bit 4GB DDR3L DIMM
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- PCIe
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- One on-board PCIe slot.
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- Two on-board PCIe Mini-PCIe connectors.
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- IFC/Local Bus
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- NOR: 128MB 16-bit NOR Flash
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- NAND: 1GB 8-bit NAND flash
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- CPLD: for system controlling with programable header on-board
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- USB
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- Supports two USB 2.0 ports with integrated PHYs
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- Two type A ports with 5V@1.5A per port.
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- SDHC
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- one SD connector supporting 1.8V/3.3V via J53.
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- SPI
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- On-board 64MB SPI flash
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- Other
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- Two Serial ports
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- Four I2C ports
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T1023RDB board Overview
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-----------------------
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- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
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- CoreNet fabric supporting coherent and noncoherent transactions with
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prioritization and bandwidth allocation
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- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
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- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
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- Ethernet interfaces:
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- one 1G RGMII port on-board(RTL8211FS PHY)
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- one 1G SGMII port on-board(RTL8211FS PHY)
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- one 2.5G SGMII port on-board(AQR105 PHY)
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- PCIe: Two Mini-PCIe connectors on-board.
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- SerDes: 4 lanes up to 10.3125GHz
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- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
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- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
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- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
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- USB: one Type-A USB 2.0 port with internal PHY
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- eSDHC: support SD/MMC and eMMC card
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- 256Kbit M24256 I2C EEPROM
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- RTC: Real-time clock DS1339U on I2C bus
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- UART: one serial port on-board with RJ45 connector
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- Debugging: JTAG/COP for T1023 debugging
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Memory map on T1024RDB
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----------------------
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Start Address End Address Description Size
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0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
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0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
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0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
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0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
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0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
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0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
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0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
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0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
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0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
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0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
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0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
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0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
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0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
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0x0_0000_0000 0x0_ffff_ffff DDR 4GB
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128MB NOR Flash Memory Layout
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-----------------------------
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Start Address End Address Definition Max size
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0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
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0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
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0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
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0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
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0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB
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0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB
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0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB
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0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB
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0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB
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0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
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0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB
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0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB
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0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
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0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
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0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
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0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
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0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
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0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB
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0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB
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0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB
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0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB
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0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB
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0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
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0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB
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0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB
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0xE8000000 0xE801FFFF RCW (current bank) 128KB
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T1024/T1023 Clock frequency
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---------------------------
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BIN Core DDR Platform FMan
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Bin1: 1400MHz 1600MT/s 400MHz 700MHz
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Bin2: 1200MHz 1600MT/s 400MHz 600MHz
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Bin3: 1000MHz 1600MT/s 400MHz 500MHz
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Software configurations and board settings
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------------------------------------------
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1. NOR boot:
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a. build NOR boot image
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$ make T1024RDB_defconfig
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$ make
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b. program u-boot.bin image to NOR flash
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=> tftp 1000000 u-boot.bin
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=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
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on T1024RDB:
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set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
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on T1023RDB:
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set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
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Switching between default bank0 and alternate bank4 on NOR flash
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To change boot source to vbank4:
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on T1024RDB:
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via software: run command 'cpld reset altbank' in U-Boot.
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via DIP-switch: set SW3[5:7] = '100'
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on T1023RDB:
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via software: run command 'switch bank4' in U-Boot.
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via DIP-switch: set SW3[5:7] = '100'
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To change boot source to vbank0:
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on T1024RDB:
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via software: run command 'cpld reset' in U-Boot.
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via DIP-Switch: set SW3[5:7] = '000'
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on T1023RDB:
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via software: run command 'switch bank0' in U-Boot.
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via DIP-switch: set SW3[5:7] = '000'
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2. NAND Boot:
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a. build PBL image for NAND boot
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$ make T1024RDB_NAND_defconfig
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$ make
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b. program u-boot-with-spl-pbl.bin to NAND flash
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> nand erase 0 $filesize
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=> nand write 1000000 0 $filesize
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set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
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3. SPI Boot:
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a. build PBL image for SPI boot
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$ make T1024RDB_SPIFLASH_defconfig
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$ make
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b. program u-boot-with-spl-pbl.bin to SPI flash
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> sf probe 0
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=> sf erase 0 100000
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=> sf write 1000000 0 $filesize
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=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
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=> sf erase 100000 100000
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=> sf write 1000000 110000 20000
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set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
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4. SD Boot:
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a. build PBL image for SD boot
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$ make T1024RDB_SDCARD_defconfig
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$ make
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b. program u-boot-with-spl-pbl.bin to SD/MMC card
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> mmc write 1000000 8 0x7f0
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=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
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=> mmc write 1000000 0x820 80
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set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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SW3[3] = '1' for SD card(or 'switch sd' by software)
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SW3[3] = '0' for eMMC (or 'switch emmc' by software)
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2-stage NAND/SPI/SD boot loader
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-------------------------------
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PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
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SPL further initializes DDR using SPD and environment variables
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and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
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Finally SPL transers control to U-Boot for futher booting.
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SPL has following features:
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- Executes within 256K
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- No relocation required
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Run time view of SPL framework
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-------------------------------------------------
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|Area | Address |
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-------------------------------------------------
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|SecureBoot header | 0xFFFC0000 (32KB) |
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-------------------------------------------------
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|GD, BD | 0xFFFC8000 (4KB) |
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-------------------------------------------------
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|ENV | 0xFFFC9000 (8KB) |
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-------------------------------------------------
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|HEAP | 0xFFFCB000 (30KB) |
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-------------------------------------------------
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|STACK | 0xFFFD8000 (22KB) |
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-------------------------------------------------
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|U-Boot SPL | 0xFFFD8000 (160KB) |
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-------------------------------------------------
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NAND Flash memory Map on T1024RDB
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-------------------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF U-Boot 1MB(2 block)
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0x100000 0x17FFFF U-Boot env 512KB(1 block)
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0x180000 0x1FFFFF FMAN Ucode 512KB(1 block)
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0x200000 0x27FFFF QE Firmware 512KB(1 block)
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NAND Flash memory Map on T1023RDB
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----------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF U-Boot 1MB
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0x100000 0x15FFFF U-Boot env 8KB
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0x160000 0x17FFFF FMAN Ucode 128KB
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SD Card memory Map on T102xRDB
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----------------------------------------------------
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Block #blocks Definition Size
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0x008 2048 U-Boot img 1MB
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0x800 0016 U-Boot env 8KB
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0x820 0256 FMAN Ucode 128KB
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0x920 0256 QE Firmware 128KB(only T1024RDB)
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64MB SPI Flash memory Map on T102xRDB
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----------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF U-Boot img 1MB
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0x100000 0x101FFF U-Boot env 8KB
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0x110000 0x12FFFF FMAN Ucode 128KB
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0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB)
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0x300000 0x3FFFFF device tree 128KB
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0x400000 0x9FFFFF Linux kernel 6MB
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0xa00000 0x3FFFFFF rootfs 54MB
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For more details, please refer to T1024RDB/T1023RDB User Guide
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and Freescale QorIQ SDK Infocenter document.
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