Overview
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=========
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The P2041 Processor combines four Power Architecture processor cores
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with high-performance datapath acceleration architecture(DPAA), CoreNet
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fabric infrastructure, as well as network and peripheral bus interfaces
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required for networking, telecom/datacom, wireless infrastructure, and
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military/aerospace applications.
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P2041RDB board is a quad core platform supporting the P2041 processor
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of QorIQ DPAA series.
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Boot from NOR flash
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===================
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1. Build image
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make P2041RDB_config
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make all
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2. Program image
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=> tftp 1000000 u-boot.bin
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=> protect off all
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=> erase eff40000 efffffff
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=> cp.b 1000000 eff40000 c0000
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3. Program RCW
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=> tftp 1000000 rcw.bin
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=> protect off all
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=> erase e8000000 e801ffff
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=> cp.b 1000000 e8000000 50
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4. Program FMAN Firmware ucode
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=> tftp 1000000 ucode.bin
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=> protect off all
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=> erase eff00000 eff3ffff
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=> cp.b 1000000 eff00000 2000
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5. Change DIP-switch
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SW1[1-5] = 10110
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Note: 1 stands for 'on', 0 stands for 'off'
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Boot from SDCard
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===================
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1. Build image
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make P2041RDB_SDCARD_config
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make all
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2. Generate PBL imge
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Use PE tool to produce a image used to be programed to
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SDCard which contains RCW and U-Boot image.
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3. Program the PBL image to SDCard
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=> tftp 1000000 pbl_sd.bin
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=> mmcinfo
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=> mmc write 1000000 8 672
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4. Program FMAN Firmware ucode
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=> tftp 1000000 ucode.bin
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=> mmc write 1000000 690 10
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5. Change DIP-switch
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SW1[1-5] = 01100
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Note: 1 stands for 'on', 0 stands for 'off'
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Boot from SPI flash
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===================
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1. Build image
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make P2041RDB_SPIFLASH_config
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make all
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2. Generate PBL imge
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Use PE tool to produce a image used to be programed to
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SPI flash which contains RCW and U-Boot image.
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3. Program the PBL image to SPI flash
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=> tftp 1000000 pbl_spi.bin
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=> spi probe 0
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=> sf erase 0 100000
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=> sf write 1000000 0 $filesize
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4. Program FMAN Firmware ucode
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=> tftp 1000000 ucode.bin
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=> sf erase 110000 10000
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=> sf write 1000000 110000 $filesize
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5. Change DIP-switch
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SW1[1-5] = 10100
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Note: 1 stands for 'on', 0 stands for 'off'
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CPLD command
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============
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The CPLD is used to control the power sequence and some serdes lane
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mux function.
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cpld reset - hard reset to default bank
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cpld reset altbank - reset to alternate bank
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cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
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lane 6: 0 -> slot1 (Default)
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1 -> SGMII
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lane a: 0 -> slot2 (Default)
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1 -> AURORA
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lane c: 0 -> slot2 (Default)
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1 -> SATA0
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lane d: 0 -> slot2 (Default)
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1 -> SATA1
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Using the Device Tree Source File
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=================================
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To create the DTB (Device Tree Binary) image file, use a command
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similar to this:
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dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
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Or use the following command:
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{linux-2.6}/make p2041rdb.dtb ARCH=powerpc
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then the dtb file will be generated under the following directory:
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{linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
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Booting Linux
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=============
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Place a linux uImage in the TFTP disk area.
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tftp 1000000 uImage
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tftp 2000000 rootfs.ext2.gz.uboot
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tftp 3000000 p2041rdb.dtb
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bootm 1000000 2000000 3000000
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