Overview
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--------
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- BSC9131 is integrated device that targets Femto base station market.
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It combines Power Architecture e500v2 and DSP StarCore SC3850 core
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technologies with MAPLE-B2F baseband acceleration processing elements.
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- It's MAPLE disabled personality is called 9231.
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The BSC9131 SoC includes the following function and features:
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. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
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L2 cache
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. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
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. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
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Processing (MAPLE-B2F)
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. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
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Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
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and CRC algorithms
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. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
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Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
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operations
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. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
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ECC, up to 400-MHz clock/800 MHz data rate
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. Dedicated security engine featuring trusted boot
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. DMA controller
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. OCNDMA with four bidirectional channels
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. Interfaces
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. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
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including IEEE 1588. v2 hardware support and virtualization (eTSEC)
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. eTSEC 1 supports RGMII/RMII
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. eTSEC 2 supports RGMII
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. High-speed USB 2.0 host and device controller with ULPI interface
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. Enhanced secure digital (SD/MMC) host controller (eSDHC)
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. Antenna interface controller (AIC), supporting three industry standard
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JESD207/three custom ADI RF interfaces (two dual port and one single port)
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and three MAXIM's MaxPHY serial interfaces
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. ADI lanes support both full duplex FDD support and half duplex TDD support
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. Universal Subscriber Identity Module (USIM) interface that facilitates
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communication to SIM cards or Eurochip pre-paid phone cards
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. TDM with one TDM port
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. Two DUART, four eSPI, and two I2C controllers
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. Integrated Flash memory controller (IFC)
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. TDM with 256 channels
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. GPIO
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. Sixteen 32-bit timers
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The e500 core subsystem within the Power Architecture consists of the following:
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. 32-Kbyte L1 instruction cache
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. 32-Kbyte L1 data cache
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. 256-Kbyte L2 cache/L2 memory/L2 stash
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. programmable interrupt controller (PIC)
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. Debug support
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. Timers
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The SC3850 core subsystem consists of the following:
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. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
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. 32 Kbyte 8-way level 1 data cache (L1 DCache)
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. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
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. Memory management unit (MMU)
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. Enhanced programmable interrupt controller (EPIC)
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. Debug and profiling unit (DPU)
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. Two 32-bit timers
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BSC9131RDB board Overview
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-------------------------
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1Gbyte DDR3 (on board DDR)
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128Mbyte 2K page size NAND Flash
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256 Kbit M24256 I2C EEPROM
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128 Mbit SPI Flash memory
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USB-ULPI
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eTSEC1: Connected to RGMII PHY
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eTSEC2: Connected to RGMII PHY
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DUART interface: supports one UARTs up to 115200 bps for console display
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USIM connector
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Frequency Combinations Supported
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--------------------------------
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Core MHz/CCB MHz/DDR(MT/s)
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1. 1000/500/800
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2. 800/400/667
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Boot Methods Supported
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-----------------------
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1. NAND Flash
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2. SPI Flash
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Default Boot Method
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--------------------
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NAND boot
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Building U-Boot
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--------------
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To build the U-Boot for BSC9131RDB:
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1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
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make BSC9131RDB_NAND
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2. NAND Flash with sysclk 100MHz(J16 on RDB open)
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make BSC9131RDB_NAND_SYSCLK100
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3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
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make BSC9131RDB_SPIFLASH
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4. SPI Flash with sysclk 100MHz(J16 on RDB open)
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make BSC9131RDB_SPIFLASH_SYSCLK100
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Memory map
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-----------
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0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
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0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
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0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
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0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K
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0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K
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0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
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0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
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0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
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0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
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0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
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DDR Memory map
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---------------
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0x0000_0000 0x36FF_FFFF Memory passed onto Linux
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0x3700_0000 0x37FF_FFFF PowerPC-DSP shared control area
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0x3800_0000 0x4FFF_FFFF DSP Private area
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Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
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data communcation between PowerPC and DSP core.
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Rest is PowerPC private area.
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Flashing Images
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---------------
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To place a new U-Boot image in the NAND flash and then boot
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with that new image temporarily, use this:
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tftp 1000000 u-boot-nand.bin
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nand erase 0 100000
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nand write 1000000 0 100000
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reset
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Using the Device Tree Source File
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---------------------------------
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To create the DTB (Device Tree Binary) image file,
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use a command similar to this:
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dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
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Likely, that .dts file will come from here;
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linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
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Booting Linux
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-------------
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Place a linux uImage in the TFTP disk area.
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tftp 1000000 uImage
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tftp 2000000 rootfs.ext2.gz.uboot
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tftp c00000 bsc9131rdb.dtb
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bootm 1000000 2000000 c00000
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