/*
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* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* sd, nand
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* Enable all clocks */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020c4084 0xffffffff
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/* ddr io type */
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DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
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DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
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/* clock */
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DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
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/* control and address */
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DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
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DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
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DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
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DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
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DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be
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configured using Group Control Register:
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IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
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DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
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DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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/* data strobes */
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DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
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DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
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DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
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/* data */
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DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
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DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
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DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
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DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
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DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
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/*
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* DDR Controller Registers
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*
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* Manufacturer: IM
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* Device Part Number: IME1G16D3EEBG-15EI
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* Clock Freq.: 400MHz
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* Density per CS in Gb: 1
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* Chip Selects used: 1
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* Number of Banks: 8
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* Row address: 13
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* Column address: 10
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* Data bus width 16
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*/
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DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
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during MMDC set up */
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/*
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* Calibration setup
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*/
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DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time &
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periodic HW ZQ calibration. */
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/*
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* For target board, may need to run write leveling calibration to fine tune
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* these settings.
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*/
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DATA 4 0x021b080c 0x00000000
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/* Read DQS Gating calibration */
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DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */
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/* Read calibration */
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DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */
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/* Write calibration */
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DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */
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/*
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* read data bit delay: (3 is the reccommended default value, although out of
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* reset value is 0)
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*/
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DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */
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DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */
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DATA 4 0x021b082c 0xF3333333
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DATA 4 0x021b0830 0xF3333333
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DATA 4 0x021b08c0 0x00921012
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/* Clock Fine Tuning */
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DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */
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/* Complete calibration by forced measurement: */
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DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */
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/*
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* Calibration setup end
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*/
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/* MMDC init: */
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DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
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DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */
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DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
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DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */
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DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
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/*
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* MDMISC: RALAT kept to the high level of 5.
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* MDMISC: consider reducing RALAT if your 528MHz board design allow that.
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* Lower RALAT benefits:
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* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT
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* to 3
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* b. Small performence improvment
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*/
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DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */
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DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
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during MMDC set up */
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DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
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DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
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DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */
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DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */
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/* Mode register writes */
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DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
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DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
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DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
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DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
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DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to
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device on CS0 */
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DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
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DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */
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DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
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DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will
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enter automatically to self-refresh while the
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number of idle cycle reached. */
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DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially
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the configuration bit as initialization is
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complete) */
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