/*
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* Bluewater Systems Snapper 9260/9G20 modules
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*
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* (C) Copyright 2011 Bluewater Systems
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* Author: Andre Renaud <andre@bluewatersys.com>
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* Author: Ryan Mallon <ryan@bluewatersys.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <atmel_lcd.h>
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#include <atmel_lcdc.h>
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#include <atmel_mci.h>
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#include <dm.h>
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#include <lcd.h>
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#include <net.h>
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#ifndef CONFIG_DM_ETH
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#include <netdev.h>
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#endif
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#include <spi.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/at91sam9g45_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_emac.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_rtc.h>
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#include <asm/arch/at91_sck.h>
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#include <asm/arch/atmel_serial.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <dm/uclass-internal.h>
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#ifdef CONFIG_GURNARD_SPLASH
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#include "splash_logo.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* IO Expander pins */
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#define IO_EXP_ETH_RESET (0 << 1)
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#define IO_EXP_ETH_POWER (1 << 1)
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#ifdef CONFIG_MACB
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static void gurnard_macb_hw_init(void)
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{
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struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
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at91_periph_clk_enable(ATMEL_ID_EMAC);
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/*
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* Enable pull-up on:
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* RXDV (PA12) => MODE0 - PHY also has pull-up
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* ERX0 (PA13) => MODE1 - PHY also has pull-up
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* ERX1 (PA15) => MODE2 - PHY also has pull-up
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*/
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writel(pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA12) |
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pin_to_mask(AT91_PIN_PA13),
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&pioa->puer);
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at91_phy_reset();
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at91_macb_hw_init();
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}
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#endif
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#ifdef CONFIG_CMD_NAND
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static int gurnard_nand_hw_init(void)
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{
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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ulong flags;
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int ret;
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/* Enable CS3 as NAND/SmartMedia */
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setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
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AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
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&smc->cs[3].cycle);
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#ifdef CONFIG_SYS_NAND_DBW_16
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flags = AT91_SMC_MODE_DBW_16;
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#else
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flags = AT91_SMC_MODE_DBW_8;
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#endif
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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flags |
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AT91_SMC_MODE_TDF_CYCLE(3),
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&smc->cs[3].mode);
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ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
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if (ret)
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return ret;
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gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
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/* Enable NandFlash */
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ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
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if (ret)
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return ret;
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gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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return 0;
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}
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#endif
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#ifdef CONFIG_GURNARD_SPLASH
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static void lcd_splash(int width, int height)
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{
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u16 colour;
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int x, y;
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u16 *base_addr = (u16 *)gd->video_bottom;
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memset(base_addr, 0xff, width * height * 2);
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/*
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* Blit the logo to the center of the screen
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*/
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for (y = 0; y < BMP_LOGO_HEIGHT; y++) {
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for (x = 0; x < BMP_LOGO_WIDTH; x++) {
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int posx, posy;
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colour = bmp_logo_palette[bmp_logo_bitmap[
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y * BMP_LOGO_WIDTH + x]];
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posx = x + (width - BMP_LOGO_WIDTH) / 2;
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posy = y;
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base_addr[posy * width + posx] = colour;
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}
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}
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}
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#endif
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#ifdef CONFIG_DM_VIDEO
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static void at91sam9g45_lcd_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
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at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
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at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
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at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
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at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
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at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
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at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
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at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
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at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
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at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
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at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
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at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
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at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
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at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
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at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
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at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
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at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
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at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
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at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
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at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
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at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
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at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
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at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
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at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
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at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
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at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
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at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
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at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
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at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
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at91_periph_clk_enable(ATMEL_ID_LCDC);
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}
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#endif
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#ifdef CONFIG_GURNARD_FPGA
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/**
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* Initialise the memory bus settings so that we can talk to the
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* memory mapped FPGA
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*/
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static int fpga_hw_init(void)
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{
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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int i;
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setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC);
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at91_set_a_periph(2, 4, 0); /* EBIA21 */
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at91_set_a_periph(2, 5, 0); /* EBIA22 */
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at91_set_a_periph(2, 6, 0); /* EBIA23 */
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at91_set_a_periph(2, 7, 0); /* EBIA24 */
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at91_set_a_periph(2, 12, 0); /* EBIA25 */
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for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */
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at91_set_a_periph(2, i, 0);
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/* configure SMC cs0 for FPGA access timing */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) |
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AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2),
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&smc->cs[0].setup);
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writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) |
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AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4),
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&smc->cs[0].pulse);
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writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
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&smc->cs[0].cycle);
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writel(AT91_SMC_MODE_BAT |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_32 |
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AT91_SMC_MODE_TDF |
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[0].mode);
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/* Do a write to within EBI_CS1 to enable the SDCK */
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writel(0, ATMEL_BASE_CS1);
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return 0;
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}
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#endif
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#ifdef CONFIG_CMD_USB
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#define USB0_ENABLE_PIN AT91_PIN_PB22
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#define USB1_ENABLE_PIN AT91_PIN_PB23
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void gurnard_usb_init(void)
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{
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at91_set_gpio_output(USB0_ENABLE_PIN, 1);
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at91_set_gpio_value(USB0_ENABLE_PIN, 0);
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at91_set_gpio_output(USB1_ENABLE_PIN, 1);
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at91_set_gpio_value(USB1_ENABLE_PIN, 0);
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}
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#endif
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#ifdef CONFIG_GENERIC_ATMEL_MCI
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int cpu_mmc_init(bd_t *bis)
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{
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return atmel_mci_init((void *)ATMEL_BASE_MCI0);
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}
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#endif
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static void gurnard_enable_console(int enable)
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{
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at91_set_gpio_output(AT91_PIN_PB14, 1);
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at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1);
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}
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void at91sam9g45_slowclock_init(void)
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{
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/*
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* On AT91SAM9G45 revC CPUs, the slow clock can be based on an
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* internal impreciseRC oscillator or an external 32kHz oscillator.
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* Switch to the latter.
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*/
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unsigned i, tmp;
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ulong *reg = (ulong *)ATMEL_BASE_SCKCR;
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tmp = readl(reg);
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if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) {
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timer_init();
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tmp |= AT91SAM9G45_SCKCR_OSC32EN;
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writel(tmp, reg);
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for (i = 0; i < 1200; i++)
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udelay(1000);
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tmp |= AT91SAM9G45_SCKCR_OSCSEL_32;
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writel(tmp, reg);
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udelay(200);
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tmp &= ~AT91SAM9G45_SCKCR_RCEN;
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writel(tmp, reg);
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}
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}
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int board_early_init_f(void)
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{
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at91_seriald_hw_init();
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gurnard_enable_console(1);
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return 0;
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}
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int board_init(void)
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{
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const char *rev_str;
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#ifdef CONFIG_CMD_NAND
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int ret;
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#endif
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at91_periph_clk_enable(ATMEL_ID_PIOA);
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at91_periph_clk_enable(ATMEL_ID_PIOB);
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at91_periph_clk_enable(ATMEL_ID_PIOC);
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at91_periph_clk_enable(ATMEL_ID_PIODE);
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at91sam9g45_slowclock_init();
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/*
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* Clear the RTC IDR to disable all IRQs. Avoid issues when Linux
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* boots with spurious IRQs.
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*/
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writel(0xffffffff, AT91_RTC_IDR);
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/* Make sure that the reset signal is attached properly */
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setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN);
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gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
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/* Address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_CMD_NAND
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ret = gurnard_nand_hw_init();
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if (ret)
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return ret;
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#endif
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#ifdef CONFIG_ATMEL_SPI
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at91_spi0_hw_init(1 << 4);
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#endif
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#ifdef CONFIG_MACB
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gurnard_macb_hw_init();
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#endif
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#ifdef CONFIG_GURNARD_FPGA
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fpga_hw_init();
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#endif
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#ifdef CONFIG_CMD_USB
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gurnard_usb_init();
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#endif
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#ifdef CONFIG_CMD_MMC
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at91_set_A_periph(AT91_PIN_PA12, 0);
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at91_set_gpio_output(AT91_PIN_PA8, 1);
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at91_set_gpio_value(AT91_PIN_PA8, 0);
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at91_mci_hw_init();
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#endif
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#ifdef CONFIG_DM_VIDEO
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at91sam9g45_lcd_hw_init();
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at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
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/* Select the second timing index for board rev 2 */
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rev_str = env_get("board_rev");
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if (rev_str && !strncmp(rev_str, "2", 1)) {
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struct udevice *dev;
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uclass_find_first_device(UCLASS_VIDEO, &dev);
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if (dev) {
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struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
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plat->timing_index = 1;
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}
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}
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#endif
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return 0;
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}
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int board_late_init(void)
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{
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u_int8_t env_enetaddr[8];
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char *env_str;
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char *end;
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int i;
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/*
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* Set MAC address so we do not need to init Ethernet before Linux
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* boot
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*/
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env_str = env_get("ethaddr");
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if (env_str) {
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struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC;
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/* Parse MAC address */
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for (i = 0; i < 6; i++) {
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env_enetaddr[i] = env_str ?
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simple_strtoul(env_str, &end, 16) : 0;
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if (env_str)
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env_str = (*end) ? end+1 : end;
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}
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/* Set hardware address */
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writel(env_enetaddr[0] | env_enetaddr[1] << 8 |
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env_enetaddr[2] << 16 | env_enetaddr[3] << 24,
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&emac->sa2l);
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writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h);
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printf("MAC: %s\n", env_get("ethaddr"));
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} else {
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/* Not set in environment */
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printf("MAC: not set\n");
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}
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#ifdef CONFIG_GURNARD_SPLASH
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lcd_splash(480, 272);
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#endif
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return 0;
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}
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#ifndef CONFIG_DM_ETH
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int board_eth_init(bd_t *bis)
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{
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return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0);
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}
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#endif
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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void reset_phy(void)
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{
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}
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/* SPI chip select control - only used for FPGA programming */
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#ifdef CONFIG_ATMEL_SPI
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* We don't use chipselects for FPGA programming */
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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/* We don't use chipselects for FPGA programming */
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}
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#endif /* CONFIG_ATMEL_SPI */
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static struct atmel_serial_platdata at91sam9260_serial_plat = {
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.base_addr = ATMEL_BASE_DBGU,
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};
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U_BOOT_DEVICE(at91sam9260_serial) = {
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.name = "serial_atmel",
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.platdata = &at91sam9260_serial_plat,
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};
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