/*
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* Copyright (C) 2014, Barco (www.barco.com)
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include "platinum.h"
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DECLARE_GLOBAL_DATA_PTR;
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iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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iomux_v3_cfg_t nfc_pads[] = {
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MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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struct fsl_esdhc_cfg usdhc_cfg[] = {
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{ USDHC3_BASE_ADDR },
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};
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void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* config gpmi nand iomux */
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imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
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/* config gpmi and bch clock to 100 MHz */
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clrsetbits_le32(&mxc_ccm->cs2cdr,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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int board_ehci_hcd_init(int port)
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{
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return 0;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) {
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unsigned sd3_cd = IMX_GPIO_NR(7, 0);
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gpio_direction_input(sd3_cd);
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return !gpio_get_value(sd3_cd);
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}
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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void board_init_gpio(void)
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{
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platinum_init_gpio();
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}
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void board_init_gpmi_nand(void)
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{
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setup_gpmi_nand();
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}
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void board_init_i2c(void)
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{
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platinum_setup_i2c();
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}
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void board_init_spi(void)
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{
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platinum_setup_spi();
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}
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void board_init_uart(void)
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{
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platinum_setup_uart();
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}
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void board_init_usb(void)
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{
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platinum_init_usb();
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}
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void board_init_finished(void)
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{
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platinum_init_finished();
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}
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int board_phy_config(struct phy_device *phydev)
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{
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return platinum_phy_config(phydev);
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}
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int board_eth_init(bd_t *bis)
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{
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return cpu_eth_init(bis);
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}
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int board_early_init_f(void)
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{
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board_init_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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board_init_spi();
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board_init_i2c();
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board_init_gpmi_nand();
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board_init_gpio();
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board_init_usb();
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board_init_finished();
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: " CONFIG_PLATINUM_BOARD "\n");
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return 0;
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}
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static const struct boot_mode board_boot_modes[] = {
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/* NAND */
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{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
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/* 4 bit bus width */
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{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
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{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
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{ NULL, 0 },
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};
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int misc_init_r(void)
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{
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add_board_boot_modes(board_boot_modes);
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return 0;
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}
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