/*
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* Copyright (C) 2012 - 2013 Atmel Corporation
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* Bo Shen <voice.shen@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sama5d3_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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#include <debug_uart.h>
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#include <lcd.h>
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#include <linux/ctype.h>
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#include <atmel_hlcdc.h>
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#include <phy.h>
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#include <micrel.h>
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#include <spl.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/at91_wdt.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_NAND_ATMEL
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void sama5d3xek_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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at91_periph_clk_enable(ATMEL_ID_SMC);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
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&smc->cs[3].cycle);
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writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
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AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
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AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
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AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(3),
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&smc->cs[3].mode);
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}
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#endif
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#ifdef CONFIG_MTD_NOR_FLASH
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static void sama5d3xek_nor_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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at91_periph_clk_enable(ATMEL_ID_SMC);
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/* Configure SMC CS0 for NOR flash */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[0].setup);
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writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
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AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
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&smc->cs[0].pulse);
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writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
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&smc->cs[0].cycle);
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writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) |
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AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) |
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AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)|
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AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_16 |
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AT91_SMC_MODE_TDF_CYCLE(1),
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&smc->cs[0].mode);
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/* Address pin (A1 ~ A23) configuration */
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0);
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0);
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/* CS0 pin configuration */
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at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0);
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}
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#endif
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#ifdef CONFIG_CMD_USB
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static void sama5d3xek_usb_hw_init(void)
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{
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at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
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at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
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at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
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}
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#endif
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#ifdef CONFIG_GENERIC_ATMEL_MCI
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static void sama5d3xek_mci_hw_init(void)
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{
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at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
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}
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#endif
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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.vl_col = 800,
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.vl_row = 480,
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.vl_clk = 24000000,
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.vl_bpix = LCD_BPP,
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.vl_tft = 1,
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.vl_hsync_len = 128,
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.vl_left_margin = 64,
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.vl_right_margin = 64,
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.vl_vsync_len = 2,
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.vl_upper_margin = 22,
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.vl_lower_margin = 21,
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.mmio = ATMEL_BASE_LCDC,
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};
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void lcd_enable(void)
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{
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}
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void lcd_disable(void)
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{
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}
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static void sama5d3xek_lcd_hw_init(void)
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{
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gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
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/* The higher 8 bit of LCD is board related */
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at91_pio3_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
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at91_pio3_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
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at91_pio3_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
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at91_pio3_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
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at91_pio3_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
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at91_pio3_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
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at91_pio3_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
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at91_pio3_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
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/* Configure lower 16 bit of LCD and enable clock */
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at91_lcd_hw_init();
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}
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#ifdef CONFIG_LCD_INFO
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#include <nand.h>
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#include <version.h>
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void lcd_show_board_info(void)
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{
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ulong dram_size;
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uint64_t nand_size;
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int i;
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char temp[32];
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lcd_printf("%s\n", U_BOOT_VERSION);
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lcd_printf("(C) 2013 ATMEL Corp\n");
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lcd_printf("at91@atmel.com\n");
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lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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dram_size += gd->bd->bi_dram[i].size;
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nand_size = 0;
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#ifdef CONFIG_NAND_ATMEL
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_size += get_nand_dev_by_index(i)->size;
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#endif
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lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
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dram_size >> 20, nand_size >> 20);
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}
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#endif /* CONFIG_LCD_INFO */
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#endif /* CONFIG_LCD */
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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at91_seriald_hw_init();
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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#endif
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return 0;
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}
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#endif
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_NAND_ATMEL
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sama5d3xek_nand_hw_init();
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#endif
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#ifdef CONFIG_MTD_NOR_FLASH
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sama5d3xek_nor_hw_init();
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#endif
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#ifdef CONFIG_CMD_USB
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sama5d3xek_usb_hw_init();
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#endif
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#ifdef CONFIG_GENERIC_ATMEL_MCI
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sama5d3xek_mci_hw_init();
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#endif
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#ifdef CONFIG_LCD
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if (has_lcdc())
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sama5d3xek_lcd_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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const int MAX_STR_LEN = 32;
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char name[MAX_STR_LEN], *p;
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int i;
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strncpy(name, get_cpu_name(), MAX_STR_LEN);
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for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++)
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*p = tolower(*p);
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strcat(name, "ek.dtb");
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env_set("dtb_name", name);
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#endif
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return 0;
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}
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#endif
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/* SPL */
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#ifdef CONFIG_SPL_BUILD
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void spl_board_init(void)
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{
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#if CONFIG_SYS_USE_NANDFLASH
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sama5d3xek_nand_hw_init();
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#endif
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}
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static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
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{
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ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
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ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
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ATMEL_MPDDRC_CR_ENRDM_ON |
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ATMEL_MPDDRC_CR_NB_8BANKS |
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ATMEL_MPDDRC_CR_NDQS_DISABLED |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
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ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
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/*
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* As the DDR2-SDRAm device requires a refresh time is 7.8125us
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* when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
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*/
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ddr2->rtr = 0x411;
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ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
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8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
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ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
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200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
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28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
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26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
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ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
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7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
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8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
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}
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void mem_init(void)
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{
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struct atmel_mpddrc_config ddr2;
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ddr2_conf(&ddr2);
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/* Enable MPDDR clock */
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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at91_system_clk_enable(AT91_PMC_DDR);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
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}
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void at91_pmc_init(void)
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{
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u32 tmp;
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tmp = AT91_PMC_PLLAR_29 |
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
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AT91_PMC_PLLXR_MUL(43) |
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AT91_PMC_PLLXR_DIV(1);
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at91_plla_init(tmp);
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at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
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tmp = AT91_PMC_MCKR_MDIV_4 |
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AT91_PMC_MCKR_CSS_PLLA;
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at91_mck_init(tmp);
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}
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#endif
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