/*
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* (C) Copyright 2002-2013
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* Eric Jarrige <eric.jarrige@armadeus.org>
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*
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* based on the files by
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com
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* and
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* Keith Outwater, keith_outwater@mvis.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <command.h>
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#include <config.h>
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#include "fpga.h"
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#include <spartan3.h>
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#include "apf27.h"
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/*
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* Note that these are pointers to code that is in Flash. They will be
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* relocated at runtime.
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* Spartan2 code is used to download our Spartan 3 :) code is compatible.
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* Just take care about the file size
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*/
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xilinx_spartan3_slave_parallel_fns fpga_fns = {
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fpga_pre_fn,
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fpga_pgm_fn,
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fpga_init_fn,
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NULL,
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fpga_done_fn,
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fpga_clk_fn,
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fpga_cs_fn,
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fpga_wr_fn,
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fpga_rdata_fn,
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fpga_wdata_fn,
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fpga_busy_fn,
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fpga_abort_fn,
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fpga_post_fn,
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};
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xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
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{xilinx_spartan3,
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slave_parallel,
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1196128l/8,
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(void *)&fpga_fns,
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0,
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&spartan3_op,
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"3s200aft256"}
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};
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/*
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* Initialize GPIO port B before download
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*/
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int fpga_pre_fn(int cookie)
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{
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/* Initialize GPIO pins */
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gpio_set_value(ACFG_FPGA_PWR, 1);
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imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
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imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
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imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
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imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
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imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
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imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
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imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO);
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gpio_set_value(ACFG_FPGA_RESET, 1);
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imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
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imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
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gpio_set_value(ACFG_FPGA_PRG, 1);
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gpio_set_value(ACFG_FPGA_CLK, 1);
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gpio_set_value(ACFG_FPGA_RW, 1);
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gpio_set_value(ACFG_FPGA_CS, 1);
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gpio_set_value(ACFG_FPGA_SUSPEND, 0);
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gpio_set_value(ACFG_FPGA_PWR, 0);
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udelay(30000); /*wait until supply started*/
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return cookie;
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}
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/*
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* Set the FPGA's active-low program line to the specified level
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*/
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int fpga_pgm_fn(int assert, int flush, int cookie)
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{
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debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
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assert ? "high" : "low");
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gpio_set_value(ACFG_FPGA_PRG, !assert);
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return assert;
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}
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/*
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* Set the FPGA's active-high clock line to the specified level
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*/
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int fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
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assert_clk ? "high" : "low");
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gpio_set_value(ACFG_FPGA_CLK, !assert_clk);
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return assert_clk;
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}
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/*
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* Test the state of the active-low FPGA INIT line. Return 1 on INIT
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* asserted (low).
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*/
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int fpga_init_fn(int cookie)
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{
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int value;
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debug("%s:%d: INIT check... ", __func__, __LINE__);
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value = gpio_get_value(ACFG_FPGA_INIT);
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/* printf("init value read %x",value); */
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#ifdef CONFIG_SYS_FPGA_IS_PROTO
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return value;
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#else
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return !value;
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#endif
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}
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/*
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* Test the state of the active-high FPGA DONE pin
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*/
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int fpga_done_fn(int cookie)
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{
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debug("%s:%d: DONE check... %s", __func__, __LINE__,
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gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low");
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return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL;
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}
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/*
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* Set the FPGA's wr line to the specified level
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*/
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int fpga_wr_fn(int assert_write, int flush, int cookie)
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{
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debug("%s:%d: FPGA RW... %s ", __func__, __LINE__,
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assert_write ? "high" : "low");
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gpio_set_value(ACFG_FPGA_RW, !assert_write);
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return assert_write;
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}
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int fpga_cs_fn(int assert_cs, int flush, int cookie)
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{
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debug("%s:%d: FPGA CS %s ", __func__, __LINE__,
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assert_cs ? "high" : "low");
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gpio_set_value(ACFG_FPGA_CS, !assert_cs);
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return assert_cs;
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}
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int fpga_rdata_fn(unsigned char *data, int cookie)
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{
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debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__,
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*((char *)ACFG_FPGA_RDATA));
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*data = (unsigned char)
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((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF);
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return *data;
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}
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int fpga_wdata_fn(unsigned char data, int flush, int cookie)
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{
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debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__,
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data);
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*((unsigned short *)ACFG_FPGA_WDATA) = data;
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return data;
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}
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int fpga_abort_fn(int cookie)
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{
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return fpga_post_fn(cookie);
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}
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int fpga_busy_fn(int cookie)
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{
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return 1;
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}
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int fpga_post_fn(int cookie)
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{
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debug("%s:%d: FPGA POST ", __func__, __LINE__);
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imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN);
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imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN);
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imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN);
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gpio_set_value(ACFG_FPGA_PRG, 1);
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gpio_set_value(ACFG_FPGA_RESET, 0);
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imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
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return cookie;
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}
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void apf27_fpga_setup(void)
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{
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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struct system_control_regs *system =
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(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
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/* Configure FPGA CLKO */
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writel(ACFG_CCSR_VAL, &pll->ccsr);
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/* Configure strentgh for FPGA */
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writel(ACFG_DSCR10_VAL, &system->dscr10);
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writel(ACFG_DSCR3_VAL, &system->dscr3);
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writel(ACFG_DSCR7_VAL, &system->dscr7);
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writel(ACFG_DSCR2_VAL, &system->dscr2);
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}
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/*
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* Initialize the fpga. Return 1 on success, 0 on failure.
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*/
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void APF27_init_fpga(void)
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{
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int i;
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apf27_fpga_setup();
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fpga_init();
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for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
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debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
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fpga_add(fpga_xilinx, &fpga[i]);
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}
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return;
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}
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