/*
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* (C) Copyright 2011
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <contact@8051projects.net>
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*
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* Based on Aspenite:
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mvmfp.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/mfp.h>
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#include <asm/arch/armada100.h>
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#include <asm/gpio.h>
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#include <miiphy.h>
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#include <asm/mach-types.h>
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#ifdef CONFIG_ARMADA100_FEC
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#include <net.h>
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#include <netdev.h>
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#endif /* CONFIG_ARMADA100_FEC */
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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u32 mfp_cfg[] = {
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/* I2C */
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MFP105_CI2C_SDA,
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MFP106_CI2C_SCL,
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/* Enable Console on UART3 */
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MFPO8_UART3_TXD,
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MFPO9_UART3_RXD,
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/* Ethernet PHY Interface */
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MFP086_ETH_TXCLK,
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MFP087_ETH_TXEN,
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MFP088_ETH_TXDQ3,
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MFP089_ETH_TXDQ2,
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MFP090_ETH_TXDQ1,
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MFP091_ETH_TXDQ0,
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MFP092_ETH_CRS,
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MFP093_ETH_COL,
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MFP094_ETH_RXCLK,
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MFP095_ETH_RXER,
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MFP096_ETH_RXDQ3,
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MFP097_ETH_RXDQ2,
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MFP098_ETH_RXDQ1,
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MFP099_ETH_RXDQ0,
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MFP100_ETH_MDC,
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MFP101_ETH_MDIO,
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MFP103_ETH_RXDV,
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/* SSP2 */
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MFP107_SSP2_RXD,
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MFP108_SSP2_TXD,
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MFP110_SSP2_CS,
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MFP111_SSP2_CLK,
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MFP_EOC /*End of configuration*/
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};
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/* configure MFP's */
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mfp_config(mfp_cfg);
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return 0;
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}
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int board_init(void)
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{
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struct armd1apb2_registers *apb2_regs =
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(struct armd1apb2_registers *)ARMD1_APBC2_BASE;
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/* arch number of Board */
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gd->bd->bi_arch_number = MACH_TYPE_GPLUGD;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
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/* Assert PHY_RST# */
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gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
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udelay(10);
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/* Deassert PHY_RST# */
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gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
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/* Enable SSP2 clock */
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writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
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return 0;
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}
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#ifdef CONFIG_ARMADA100_FEC
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int board_eth_init(bd_t *bis)
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{
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struct armd1apmu_registers *apmu_regs =
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(struct armd1apmu_registers *)ARMD1_APMU_BASE;
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/* Enable clock of ethernet controller */
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writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
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return armada100_fec_register(ARMD1_FEC_BASE);
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}
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#ifdef CONFIG_RESET_PHY_R
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/* Configure and initialize PHY chip 88E3015 */
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void reset_phy(void)
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{
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u16 phy_adr;
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const char *name = "armd-fec0";
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
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printf("Err..%s could not read PHY dev address\n", __func__);
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return;
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}
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/* Set Ethernet LED in TX blink mode */
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miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
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miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
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/* reset the phy */
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miiphy_reset(name, phy_adr);
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debug("88E3015 Initialized on %s\n", name);
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}
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#endif /* CONFIG_RESET_PHY_R */
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#endif /* CONFIG_ARMADA100_FEC */
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