/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_MX6SX_DDR_H__
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#define __ASM_ARCH_MX6SX_DDR_H__
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#ifndef CONFIG_MX6SX
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#error "wrong CPU"
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#endif
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#define MX6_IOM_DRAM_DQM0 0x020e02ec
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#define MX6_IOM_DRAM_DQM1 0x020e02f0
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#define MX6_IOM_DRAM_DQM2 0x020e02f4
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#define MX6_IOM_DRAM_DQM3 0x020e02f8
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#define MX6_IOM_DRAM_RAS 0x020e02fc
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#define MX6_IOM_DRAM_CAS 0x020e0300
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#define MX6_IOM_DRAM_SDODT0 0x020e0310
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#define MX6_IOM_DRAM_SDODT1 0x020e0314
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#define MX6_IOM_DRAM_SDBA2 0x020e0320
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#define MX6_IOM_DRAM_SDCKE0 0x020e0324
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#define MX6_IOM_DRAM_SDCKE1 0x020e0328
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#define MX6_IOM_DRAM_SDCLK_0 0x020e032c
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#define MX6_IOM_DRAM_RESET 0x020e0340
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#define MX6_IOM_DRAM_SDQS0 0x020e0330
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#define MX6_IOM_DRAM_SDQS1 0x020e0334
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#define MX6_IOM_DRAM_SDQS2 0x020e0338
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#define MX6_IOM_DRAM_SDQS3 0x020e033c
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#define MX6_IOM_GRP_ADDDS 0x020e05f4
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#define MX6_IOM_DDRMODE_CTL 0x020e05f8
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#define MX6_IOM_GRP_DDRPKE 0x020e05fc
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#define MX6_IOM_GRP_DDRMODE 0x020e0608
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#define MX6_IOM_GRP_B0DS 0x020e060c
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#define MX6_IOM_GRP_B1DS 0x020e0610
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#define MX6_IOM_GRP_CTLDS 0x020e0614
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#define MX6_IOM_GRP_DDR_TYPE 0x020e0618
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#define MX6_IOM_GRP_B2DS 0x020e061c
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#define MX6_IOM_GRP_B3DS 0x020e0620
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#endif /*__ASM_ARCH_MX6SX_DDR_H__ */
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