/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* provides masks and opcode images for use by code generation, emulation
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* and for instructions that older assemblers might not know about
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*/
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#ifndef _ASM_POWERPC_PPC_OPCODE_H
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#define _ASM_POWERPC_PPC_OPCODE_H
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# define stringify_in_c(...) __VA_ARGS__
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# define ASM_CONST(x) x
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#define PPC_INST_VCMPEQUD_RC 0x100000c7
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#define PPC_INST_VCMPEQUB_RC 0x10000006
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#define __PPC_RC21 (0x1 << 10)
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/* macros to insert fields into opcodes */
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#define ___PPC_RA(a) (((a) & 0x1f) << 16)
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#define ___PPC_RB(b) (((b) & 0x1f) << 11)
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#define ___PPC_RS(s) (((s) & 0x1f) << 21)
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#define ___PPC_RT(t) ___PPC_RS(t)
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#define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUD_RC | \
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___PPC_RT(vrt) | ___PPC_RA(vra) | \
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___PPC_RB(vrb) | __PPC_RC21)
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#define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUB_RC | \
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___PPC_RT(vrt) | ___PPC_RA(vra) | \
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___PPC_RB(vrb) | __PPC_RC21)
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#endif /* _ASM_POWERPC_PPC_OPCODE_H */
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