/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#include "mp_precomp.h"
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#include "../phydm_precomp.h"
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#if (RTL8723B_SUPPORT == 1)
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void
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odm_config_rf_reg_8723b(
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struct PHY_DM_STRUCT *p_dm,
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u32 addr,
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u32 data,
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enum rf_path RF_PATH,
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u32 reg_addr
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)
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{
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if (addr == 0xfe || addr == 0xffe) {
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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} else {
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odm_set_rf_reg(p_dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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/* For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25. */
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if (addr == 0xb6) {
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u32 getvalue = 0;
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u8 count = 0;
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getvalue = odm_get_rf_reg(p_dm, RF_PATH, addr, MASKDWORD);
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ODM_delay_us(1);
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while ((getvalue >> 8) != (data >> 8)) {
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count++;
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odm_set_rf_reg(p_dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
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ODM_delay_us(1);
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getvalue = odm_get_rf_reg(p_dm, RF_PATH, addr, MASKDWORD);
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PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_rf_with_header_file: [B6] getvalue 0x%x, data 0x%x, count %d\n", getvalue, data, count));
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if (count > 5)
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break;
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}
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}
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if (addr == 0xb2) {
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u32 getvalue = 0;
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u8 count = 0;
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getvalue = odm_get_rf_reg(p_dm, RF_PATH, addr, MASKDWORD);
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ODM_delay_us(1);
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while (getvalue != data) {
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count++;
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odm_set_rf_reg(p_dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
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ODM_delay_us(1);
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/* Do LCK againg */
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odm_set_rf_reg(p_dm, RF_PATH, 0x18, RFREGOFFSETMASK, 0x0fc07);
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ODM_delay_us(1);
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getvalue = odm_get_rf_reg(p_dm, RF_PATH, addr, MASKDWORD);
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PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_rf_with_header_file: [B2] getvalue 0x%x, data 0x%x, count %d\n", getvalue, data, count));
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if (count > 5)
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break;
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}
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}
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}
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}
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void
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odm_config_rf_radio_a_8723b(
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struct PHY_DM_STRUCT *p_dm,
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u32 addr,
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u32 data
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)
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{
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u32 content = 0x1000; /* RF_Content: radioa_txt */
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u32 maskfor_phy_set = (u32)(content & 0xE000);
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odm_config_rf_reg_8723b(p_dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
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PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data));
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}
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void
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odm_config_rf_radio_b_8723b(
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struct PHY_DM_STRUCT *p_dm,
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u32 addr,
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u32 data
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)
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{
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u32 content = 0x1001; /* RF_Content: radiob_txt */
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u32 maskfor_phy_set = (u32)(content & 0xE000);
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odm_config_rf_reg_8723b(p_dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
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PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", addr, data));
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}
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void
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odm_config_mac_8723b(
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struct PHY_DM_STRUCT *p_dm,
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u32 addr,
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u8 data
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)
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{
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odm_write_1byte(p_dm, addr, data);
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PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", addr, data));
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}
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void
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odm_config_bb_agc_8723b(
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struct PHY_DM_STRUCT *p_dm,
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u32 addr,
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u32 bitmask,
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u32 data
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)
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{
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odm_set_bb_reg(p_dm, addr, bitmask, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data));
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}
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void
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odm_config_bb_phy_reg_pg_8723b(
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struct PHY_DM_STRUCT *p_dm,
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u32 band,
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u32 rf_path,
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u32 tx_num,
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u32 addr,
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u32 bitmask,
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u32 data
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)
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{
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if (addr == 0xfe || addr == 0xffe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else {
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_store_tx_power_by_rate(p_dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
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#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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PHY_StoreTxPowerByRate(p_dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
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#endif
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}
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PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data));
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}
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void
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odm_config_bb_phy_8723b(
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struct PHY_DM_STRUCT *p_dm,
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u32 addr,
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u32 bitmask,
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u32 data
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)
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{
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if (addr == 0xfe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else if (addr == 0xfd)
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ODM_delay_ms(5);
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else if (addr == 0xfc)
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ODM_delay_ms(1);
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else if (addr == 0xfb)
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ODM_delay_us(50);
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else if (addr == 0xfa)
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ODM_delay_us(5);
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else if (addr == 0xf9)
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ODM_delay_us(1);
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else
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odm_set_bb_reg(p_dm, addr, bitmask, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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PHYDM_DBG(p_dm, ODM_COMP_INIT, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n", addr, data));
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}
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void
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odm_config_bb_txpwr_lmt_8723b(
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struct PHY_DM_STRUCT *p_dm,
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u8 *regulation,
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u8 *band,
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u8 *bandwidth,
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u8 *rate_section,
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u8 *rf_path,
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u8 *channel,
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u8 *power_limit
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)
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{
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_set_tx_power_limit(p_dm, regulation, band,
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bandwidth, rate_section, rf_path, channel, power_limit);
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#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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PHY_SetTxPowerLimit(p_dm, regulation, band,
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bandwidth, rate_section, rf_path, channel, power_limit);
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#endif
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}
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#endif
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