/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __HAL_DATA_H__
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#define __HAL_DATA_H__
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#if 1//def CONFIG_SINGLE_IMG
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#include "../hal/phydm/phydm_precomp.h"
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#ifdef CONFIG_BT_COEXIST
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#include <hal_btcoex.h>
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#endif
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#ifdef CONFIG_SDIO_HCI
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#include <hal_sdio.h>
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#endif
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#ifdef CONFIG_GSPI_HCI
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#include <hal_gspi.h>
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#endif
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//
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// <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
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//
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typedef enum _RT_MULTI_FUNC{
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RT_MULTI_FUNC_NONE = 0x00,
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RT_MULTI_FUNC_WIFI = 0x01,
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RT_MULTI_FUNC_BT = 0x02,
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RT_MULTI_FUNC_GPS = 0x04,
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}RT_MULTI_FUNC,*PRT_MULTI_FUNC;
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//
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// <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
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//
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typedef enum _RT_POLARITY_CTL {
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RT_POLARITY_LOW_ACT = 0,
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RT_POLARITY_HIGH_ACT = 1,
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} RT_POLARITY_CTL, *PRT_POLARITY_CTL;
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// For RTL8723 regulator mode. by tynli. 2011.01.14.
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typedef enum _RT_REGULATOR_MODE {
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RT_SWITCHING_REGULATOR = 0,
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RT_LDO_REGULATOR = 1,
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} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
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//
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// Interface type.
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//
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typedef enum _INTERFACE_SELECT_PCIE{
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INTF_SEL0_SOLO_MINICARD = 0, // WiFi solo-mCard
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INTF_SEL1_BT_COMBO_MINICARD = 1, // WiFi+BT combo-mCard
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INTF_SEL2_PCIe = 2, // PCIe Card
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} INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE;
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typedef enum _INTERFACE_SELECT_USB{
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INTF_SEL0_USB = 0, // USB
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INTF_SEL1_USB_High_Power = 1, // USB with high power PA
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INTF_SEL2_MINICARD = 2, // Minicard
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INTF_SEL3_USB_Solo = 3, // USB solo-Slim module
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INTF_SEL4_USB_Combo = 4, // USB Combo-Slim module
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INTF_SEL5_USB_Combo_MF = 5, // USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card
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} INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;
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typedef enum _RT_AMPDU_BRUST_MODE{
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RT_AMPDU_BRUST_NONE = 0,
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RT_AMPDU_BRUST_92D = 1,
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RT_AMPDU_BRUST_88E = 2,
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RT_AMPDU_BRUST_8812_4 = 3,
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RT_AMPDU_BRUST_8812_8 = 4,
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RT_AMPDU_BRUST_8812_12 = 5,
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RT_AMPDU_BRUST_8812_15 = 6,
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RT_AMPDU_BRUST_8723B = 7,
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}RT_AMPDU_BRUST,*PRT_AMPDU_BRUST_MODE;
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#define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number
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#define CHANNEL_MAX_NUMBER_2G 14
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#define CHANNEL_MAX_NUMBER_5G 54 // Please refer to "phy_GetChnlGroup8812A" and "Hal_ReadTxPowerInfo8812A"
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#define CHANNEL_MAX_NUMBER_5G_80M 7
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#define CHANNEL_GROUP_MAX 3+9 // ch1~3, ch4~9, ch10~14 total three groups
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#define MAX_PG_GROUP 13
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// Tx Power Limit Table Size
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#define MAX_REGULATION_NUM 4
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#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4
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#define MAX_2_4G_BANDWITH_NUM 2
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#define MAX_RATE_SECTION_NUM 10
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#define MAX_5G_BANDWITH_NUM 4
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#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 // CCK:1,OFDM:1, HT:4, VHT:4
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#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 // OFDM:1, HT:4, VHT:4
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//###### duplicate code,will move to ODM #########
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//#define IQK_MAC_REG_NUM 4
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//#define IQK_ADDA_REG_NUM 16
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//#define IQK_BB_REG_NUM 10
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#define IQK_BB_REG_NUM_92C 9
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#define IQK_BB_REG_NUM_92D 10
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#define IQK_BB_REG_NUM_test 6
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#define IQK_Matrix_Settings_NUM_92D 1+24+21
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//#define HP_THERMAL_NUM 8
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//###### duplicate code,will move to ODM #########
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#ifdef CONFIG_USB_RX_AGGREGATION
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typedef enum _USB_RX_AGG_MODE{
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USB_RX_AGG_DISABLE,
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USB_RX_AGG_DMA,
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USB_RX_AGG_USB,
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USB_RX_AGG_MIX
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}USB_RX_AGG_MODE;
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//#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer
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#endif
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/* For store initial value of BB register */
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typedef struct _BB_INIT_REGISTER {
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u16 offset;
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u32 value;
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} BB_INIT_REGISTER, *PBB_INIT_REGISTER;
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#define PAGE_SIZE_128 128
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#define PAGE_SIZE_256 256
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#define PAGE_SIZE_512 512
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#define HCI_SUS_ENTER 0
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#define HCI_SUS_LEAVING 1
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#define HCI_SUS_LEAVE 2
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#define HCI_SUS_ENTERING 3
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#define HCI_SUS_ERR 4
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#ifdef CONFIG_AUTO_CHNL_SEL_NHM
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typedef enum _ACS_OP {
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ACS_INIT, /*ACS - Variable init*/
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ACS_RESET, /*ACS - NHM Counter reset*/
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ACS_SELECT, /*ACS - NHM Counter Statistics */
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} ACS_OP;
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typedef enum _ACS_STATE {
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ACS_DISABLE,
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ACS_ENABLE,
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} ACS_STATE;
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struct auto_chan_sel {
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ATOMIC_T state;
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u8 ch; /* previous channel*/
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};
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#endif /*CONFIG_AUTO_CHNL_SEL_NHM*/
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#define EFUSE_FILE_UNUSED 0
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#define EFUSE_FILE_FAILED 1
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#define EFUSE_FILE_LOADED 2
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#define MACADDR_FILE_UNUSED 0
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#define MACADDR_FILE_FAILED 1
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#define MACADDR_FILE_LOADED 2
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#define KFREE_FLAG_ON BIT0
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#define KFREE_FLAG_THERMAL_K_ON BIT1
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struct kfree_data_t {
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u8 flag;
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s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];
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#ifdef CONFIG_RTL8814A
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s8 pa_bias_5g[RF_PATH_MAX];
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s8 pad_bias_5g[RF_PATH_MAX];
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#endif
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s8 thermal;
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};
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bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data);
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typedef struct hal_com_data
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{
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HAL_VERSION VersionID;
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RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
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RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
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RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
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u8 hw_init_completed;
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/****** FW related ******/
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u16 FirmwareVersion;
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u16 FirmwareVersionRev;
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u16 FirmwareSubVersion;
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u16 FirmwareSignature;
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u8 RegFWOffload;
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u8 fw_ractrl;
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u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/
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u8 LastHMEBoxNum; /* H2C - for host message to fw */
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/****** current WIFI_PHY values ******/
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WIRELESS_MODE CurrentWirelessMode;
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CHANNEL_WIDTH CurrentChannelBW;
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BAND_TYPE CurrentBandType; /* 0:2.4G, 1:5G */
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BAND_TYPE BandSet;
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u8 CurrentChannel;
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u8 CurrentCenterFrequencyIndex1;
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u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */
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u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */
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BOOLEAN bSwChnlAndSetBWInProgress;
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u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */
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u16 BasicRateSet;
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u32 ReceiveConfig;
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BOOLEAN bSwChnl;
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BOOLEAN bSetChnlBW;
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BOOLEAN bChnlBWInitialized;
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#ifdef CONFIG_AUTO_CHNL_SEL_NHM
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struct auto_chan_sel acs;
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#endif
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/****** rf_ctrl *****/
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u8 rf_chip;
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u8 rf_type;
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u8 PackageType;
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u8 NumTotalRFPath;
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/****** Debug ******/
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u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
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u8 u1ForcedIgiLb; /* forced IGI lower bound */
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u8 bDumpRxPkt;
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u8 bDumpTxPkt;
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u8 bDisableTXPowerTraining;
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/****** EEPROM setting.******/
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u8 bautoload_fail_flag;
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u8 efuse_file_status;
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u8 macaddr_file_status;
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u8 EepromOrEfuse;
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u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/
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u8 InterfaceSel; /* board type kept in eFuse */
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u16 CustomerID;
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u16 EEPROMVID;
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u16 EEPROMSVID;
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#ifdef CONFIG_USB_HCI
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u16 EEPROMPID;
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u16 EEPROMSDID;
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#endif
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#ifdef CONFIG_PCI_HCI
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u16 EEPROMDID;
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u16 EEPROMSMID;
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#endif
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u8 EEPROMCustomerID;
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u8 EEPROMSubCustomerID;
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u8 EEPROMVersion;
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u8 EEPROMRegulatory;
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u8 EEPROMThermalMeter;
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u8 EEPROMBluetoothCoexist;
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u8 EEPROMBluetoothType;
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u8 EEPROMBluetoothAntNum;
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u8 EEPROMBluetoothAntIsolation;
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u8 EEPROMBluetoothRadioShared;
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u8 bTXPowerDataReadFromEEPORM;
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u8 EEPROMMACAddr[ETH_ALEN];
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#ifdef CONFIG_RF_GAIN_OFFSET
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u8 EEPROMRFGainOffset;
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u8 EEPROMRFGainVal;
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struct kfree_data_t kfree_data;
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#endif /*CONFIG_RF_GAIN_OFFSET*/
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#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B)
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u8 adjuseVoltageVal;
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#endif
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u8 EfuseUsedPercentage;
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u16 EfuseUsedBytes;
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/*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/
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EFUSE_HAL EfuseHal;
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/*---------------------------------------------------------------------------------*/
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//3 [2.4G]
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u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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//If only one tx, only BW20 and OFDM are used.
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s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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//3 [5G]
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u8 Index5G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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u8 Index5G_BW80_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
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s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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u8 Regulation2_4G;
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u8 Regulation5G;
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u8 TxPwrInPercentage;
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/********************************
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* TX power by rate table at most 4RF path.
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* The register is
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*
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* VHT TX power by rate off setArray =
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* Band:-2G&5G = 0 / 1
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* RF: at most 4*4 = ABCD=0/1/2/3
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* CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
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**********************************/
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u8 TxPwrByRateTable;
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u8 TxPwrByRateBand;
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s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
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[TX_PWR_BY_RATE_NUM_RF]
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[TX_PWR_BY_RATE_NUM_RF]
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[TX_PWR_BY_RATE_NUM_RATE];
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//---------------------------------------------------------------------------------//
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//2 Power Limit Table
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u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
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u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
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u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
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s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
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u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
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// Power Limit Table for 2.4G
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s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM]
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[MAX_2_4G_BANDWITH_NUM]
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[MAX_RATE_SECTION_NUM]
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[CHANNEL_MAX_NUMBER_2G]
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[MAX_RF_PATH_NUM];
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// Power Limit Table for 5G
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s8 TxPwrLimit_5G[MAX_REGULATION_NUM]
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[MAX_5G_BANDWITH_NUM]
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[MAX_RATE_SECTION_NUM]
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[CHANNEL_MAX_NUMBER_5G]
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[MAX_RF_PATH_NUM];
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// Store the original power by rate value of the base of each rate section of rf path A & B
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u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]
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[TX_PWR_BY_RATE_NUM_RF]
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[MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
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u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]
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[TX_PWR_BY_RATE_NUM_RF]
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[MAX_BASE_NUM_IN_PHY_REG_PG_5G];
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// For power group
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u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
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u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
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u8 PGMaxGroup;
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// The current Tx Power Level
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u8 CurrentCckTxPwrIdx;
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u8 CurrentOfdm24GTxPwrIdx;
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u8 CurrentBW2024GTxPwrIdx;
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u8 CurrentBW4024GTxPwrIdx;
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// Read/write are allow for following hardware information variables
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u8 pwrGroupCnt;
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u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
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u32 CCKTxPowerLevelOriginalOffset;
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u8 CrystalCap;
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u8 PAType_2G;
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u8 PAType_5G;
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u8 LNAType_2G;
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u8 LNAType_5G;
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u8 ExternalPA_2G;
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u8 ExternalLNA_2G;
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u8 ExternalPA_5G;
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u8 ExternalLNA_5G;
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u8 TypeGLNA;
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u8 TypeGPA;
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u8 TypeALNA;
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u8 TypeAPA;
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u8 RFEType;
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u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
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u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
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BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; //Radio A/B/C/D
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u32 RfRegChnlVal[MAX_RF_PATH];
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//RDG enable
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BOOLEAN bRDGEnable;
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u8 RegTxPause;
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// Beacon function related global variable.
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u8 RegBcnCtrlVal;
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u8 RegFwHwTxQCtrl;
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u8 RegReg542;
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u8 RegCR_1;
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u8 Reg837;
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u16 RegRRSR;
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/****** antenna diversity ******/
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u8 CurAntenna;
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u8 AntDivCfg;
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u8 AntDetection;
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u8 TRxAntDivType;
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u8 ant_path; //for 8723B s0/s1 selection
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u32 AntennaTxPath; /* Antenna path Tx */
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u32 AntennaRxPath; /* Antenna path Rx */
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/******** PHY DM & DM Section **********/
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u8 DM_Type;
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_lock IQKSpinLock;
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u8 INIDATA_RATE[MACID_NUM_SW_LIMIT];
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/* Upper and Lower Signal threshold for Rate Adaptive*/
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int EntryMinUndecoratedSmoothedPWDB;
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int EntryMaxUndecoratedSmoothedPWDB;
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int MinUndecoratedPWDBForDM;
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DM_ODM_T odmpriv;
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u8 bIQKInitialized;
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u8 bNeedIQK;
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/******** PHY DM & DM Section **********/
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// 2010/08/09 MH Add CU power down mode.
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BOOLEAN pwrdown;
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// Add for dual MAC 0--Mac0 1--Mac1
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u32 interfaceIndex;
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#ifdef CONFIG_P2P
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u8 p2p_ps_offload;
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#endif
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/* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
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u8 bMacPwrCtrlOn;
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u8 hci_sus_state;
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u8 RegIQKFWOffload;
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struct submit_ctx iqk_sctx;
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RT_AMPDU_BRUST AMPDUBurstMode; //92C maybe not use, but for compile successfully
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u8 OutEpQueueSel;
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u8 OutEpNumber;
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#if defined (CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
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//
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// For SDIO Interface HAL related
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//
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//
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// SDIO ISR Related
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//
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// u32 IntrMask[1];
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// u32 IntrMaskToSet[1];
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// LOG_INTERRUPT InterruptLog;
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u32 sdio_himr;
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u32 sdio_hisr;
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//
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// SDIO Tx FIFO related.
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//
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// HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg
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u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
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_lock SdioTxFIFOFreePageLock;
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u8 SdioTxOQTMaxFreeSpace;
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u8 SdioTxOQTFreeSpace;
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//
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// SDIO Rx FIFO related.
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//
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u8 SdioRxFIFOCnt;
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u16 SdioRxFIFOSize;
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u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];// H, N, L, used for sdio tx aggregation max length per queue
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#endif //CONFIG_SDIO_HCI
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#ifdef CONFIG_USB_HCI
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// 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
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BOOLEAN UsbRxHighSpeedMode;
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BOOLEAN UsbTxVeryHighSpeedMode;
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u32 UsbBulkOutSize;
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BOOLEAN bSupportUSB3;
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// Interrupt relatd register information.
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u32 IntArray[3];//HISR0,HISR1,HSISR
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u32 IntrMask[3];
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u8 C2hArray[16];
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#ifdef CONFIG_USB_TX_AGGREGATION
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u8 UsbTxAggMode;
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u8 UsbTxAggDescNum;
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#endif // CONFIG_USB_TX_AGGREGATION
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#ifdef CONFIG_USB_RX_AGGREGATION
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u16 HwRxPageSize; // Hardware setting
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u32 MaxUsbRxAggBlock;
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USB_RX_AGG_MODE UsbRxAggMode;
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u8 UsbRxAggBlockCount; /* FOR USB Mode, USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed */
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u8 UsbRxAggBlockTimeout;
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u8 UsbRxAggPageCount; /* FOR DMA Mode, 8192C DMA page count*/
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u8 UsbRxAggPageTimeout;
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u8 RegAcUsbDmaSize;
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u8 RegAcUsbDmaTime;
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#endif//CONFIG_USB_RX_AGGREGATION
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#endif //CONFIG_USB_HCI
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#ifdef CONFIG_PCI_HCI
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//
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// EEPROM setting.
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//
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u32 TransmitConfig;
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u32 IntrMaskToSet[2];
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u32 IntArray[2];
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u32 IntrMask[2];
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u32 SysIntArray[1];
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u32 SysIntrMask[1];
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u32 IntrMaskReg[2];
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u32 IntrMaskDefault[2];
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BOOLEAN bL1OffSupport;
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BOOLEAN bSupportBackDoor;
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u8 bDefaultAntenna;
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u8 bInterruptMigration;
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u8 bDisableTxInt;
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u16 RxTag;
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#endif //CONFIG_PCI_HCI
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#ifdef DBG_CONFIG_ERROR_DETECT
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struct sreset_priv srestpriv;
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#endif //#ifdef DBG_CONFIG_ERROR_DETECT
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#ifdef CONFIG_BT_COEXIST
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// For bluetooth co-existance
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BT_COEXIST bt_coexist;
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#endif // CONFIG_BT_COEXIST
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#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8188F)
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#ifndef CONFIG_PCI_HCI // mutual exclusive with PCI -- so they're SDIO and GSPI
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// Interrupt relatd register information.
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u32 SysIntrStatus;
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u32 SysIntrMask;
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#endif
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#endif /*endif CONFIG_RTL8723B */
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#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
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char para_file_buf[MAX_PARA_FILE_BUF_LEN];
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char *mac_reg;
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u32 mac_reg_len;
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char *bb_phy_reg;
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u32 bb_phy_reg_len;
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char *bb_agc_tab;
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u32 bb_agc_tab_len;
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char *bb_phy_reg_pg;
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u32 bb_phy_reg_pg_len;
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char *bb_phy_reg_mp;
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u32 bb_phy_reg_mp_len;
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char *rf_radio_a;
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u32 rf_radio_a_len;
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char *rf_radio_b;
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u32 rf_radio_b_len;
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char *rf_tx_pwr_track;
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u32 rf_tx_pwr_track_len;
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char *rf_tx_pwr_lmt;
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u32 rf_tx_pwr_lmt_len;
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#endif
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#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
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s16 noise[ODM_MAX_CHANNEL_NUM];
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#endif
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u8 macid_num;
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u8 cam_entry_num;
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u8 sec_cap;
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u8 RfKFreeEnable;
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BOOLEAN bCCKinCH14;
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BB_INIT_REGISTER BBRegForRecover[6];
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} HAL_DATA_COMMON, *PHAL_DATA_COMMON;
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typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
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#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
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#define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath )
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#define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel)
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#define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type)
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#define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data))
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#define SUPPORT_HW_RADIO_DETECT(Adapter) ( RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD ||\
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RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo ||\
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RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo)
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#define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr)
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#define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse)
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#define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed)
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#define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE)
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#endif
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#ifdef CONFIG_AUTO_CHNL_SEL_NHM
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#define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))
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#define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))
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#define rtw_get_acs_channel(padapter) (GET_HAL_DATA(padapter)->acs.ch)
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#define rtw_set_acs_channel(padapter, survey_ch) (GET_HAL_DATA(padapter)->acs.ch = survey_ch)
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#endif /*CONFIG_AUTO_CHNL_SEL_NHM*/
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#endif //__HAL_DATA_H__
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