/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __PHYDMANTDIV_H__
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#define __PHYDMANTDIV_H__
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/*#define ANTDIV_VERSION "2.0" //2014.11.04*/
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/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/
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#define ANTDIV_VERSION "2.2" /*2015.01.16 Dino*/
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//1 ============================================================
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//1 Definition
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//1 ============================================================
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#define ANTDIV_INIT 0xff
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#define MAIN_ANT 1 //Ant A or Ant Main
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#define AUX_ANT 2 //AntB or Ant Aux
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#define MAX_ANT 3 // 3 for AP using
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#define ANT1_2G 0 // = ANT2_5G
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#define ANT2_2G 1 // = ANT1_5G
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//Antenna Diversty Control Type
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#define ODM_AUTO_ANT 0
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#define ODM_FIX_MAIN_ANT 1
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#define ODM_FIX_AUX_ANT 2
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#define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
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#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
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#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
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#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E)
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#define ODM_OLD_IC_ANTDIV_SUPPORT (ODM_RTL8723A|ODM_RTL8192C|ODM_RTL8192D)
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#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A)
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#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
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#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
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#define ODM_ANTDIV_2G BIT0
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#define ODM_ANTDIV_5G BIT1
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#define ANTDIV_ON 1
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#define ANTDIV_OFF 0
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#define FAT_ON 1
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#define FAT_OFF 0
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#define TX_BY_DESC 1
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#define REG 0
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#define RSSI_METHOD 0
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#define EVM_METHOD 1
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#define CRC32_METHOD 2
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#define INIT_ANTDIV_TIMMER 0
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#define CANCEL_ANTDIV_TIMMER 1
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#define RELEASE_ANTDIV_TIMMER 2
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#define CRC32_FAIL 1
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#define CRC32_OK 0
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#define Evm_RSSI_TH_High 25
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#define Evm_RSSI_TH_Low 20
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#define NORMAL_STATE_MIAN 1
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#define NORMAL_STATE_AUX 2
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#define TRAINING_STATE 3
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#define FORCE_RSSI_DIFF 10
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#define CSI_ON 1
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#define CSI_OFF 0
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#define DIVON_CSIOFF 1
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#define DIVOFF_CSION 2
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#define BDC_DIV_TRAIN_STATE 0
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#define BDC_BFer_TRAIN_STATE 1
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#define BDC_DECISION_STATE 2
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#define BDC_BF_HOLD_STATE 3
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#define BDC_DIV_HOLD_STATE 4
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#define BDC_MODE_1 1
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#define BDC_MODE_2 2
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#define BDC_MODE_3 3
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#define BDC_MODE_4 4
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#define BDC_MODE_NULL 0xff
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#define SWAW_STEP_PEAK 0
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#define SWAW_STEP_DETERMINE 1
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//1 ============================================================
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//1 structure
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//1 ============================================================
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typedef struct _SW_Antenna_Switch_
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{
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u1Byte Double_chk_flag;
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u1Byte try_flag;
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s4Byte PreRSSI;
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u1Byte CurAntenna;
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u1Byte PreAntenna;
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u1Byte RSSI_Trying;
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u1Byte TestMode;
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u1Byte bTriggerAntennaSwitch;
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u1Byte SelectAntennaMap;
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u1Byte RSSI_target;
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u1Byte reset_idx;
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u2Byte Single_Ant_Counter;
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u2Byte Dual_Ant_Counter;
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u2Byte Aux_FailDetec_Counter;
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u2Byte Retry_Counter;
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// Before link Antenna Switch check
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u1Byte SWAS_NoLink_State;
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u4Byte SWAS_NoLink_BK_Reg860;
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u4Byte SWAS_NoLink_BK_Reg92c;
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u4Byte SWAS_NoLink_BK_Reg948;
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BOOLEAN ANTA_ON; //To indicate Ant A is or not
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BOOLEAN ANTB_ON; //To indicate Ant B is on or not
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BOOLEAN Pre_Aux_FailDetec;
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BOOLEAN RSSI_AntDect_bResult;
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u1Byte Ant5G;
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u1Byte Ant2G;
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s4Byte RSSI_sum_A;
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s4Byte RSSI_sum_B;
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s4Byte RSSI_cnt_A;
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s4Byte RSSI_cnt_B;
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u8Byte lastTxOkCnt;
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u8Byte lastRxOkCnt;
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u8Byte TXByteCnt_A;
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u8Byte TXByteCnt_B;
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u8Byte RXByteCnt_A;
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u8Byte RXByteCnt_B;
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u1Byte TrafficLoad;
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u1Byte Train_time;
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u1Byte Train_time_flag;
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RT_TIMER SwAntennaSwitchTimer;
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#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
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RT_TIMER SwAntennaSwitchTimer_8723B;
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u4Byte PktCnt_SWAntDivByCtrlFrame;
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BOOLEAN bSWAntDivByCtrlFrame;
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#endif
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#if USE_WORKITEM
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RT_WORK_ITEM SwAntennaSwitchWorkitem;
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#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
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RT_WORK_ITEM SwAntennaSwitchWorkitem_8723B;
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#endif
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#endif
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#endif
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/* CE Platform use
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#ifdef CONFIG_SW_ANTENNA_DIVERSITY
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_timer SwAntennaSwitchTimer;
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u8Byte lastTxOkCnt;
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u8Byte lastRxOkCnt;
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u8Byte TXByteCnt_A;
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u8Byte TXByteCnt_B;
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u8Byte RXByteCnt_A;
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u8Byte RXByteCnt_B;
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u1Byte DoubleComfirm;
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u1Byte TrafficLoad;
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//SW Antenna Switch
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#endif
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*/
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#ifdef CONFIG_HW_ANTENNA_DIVERSITY
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//Hybrid Antenna Diversity
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u4Byte CCK_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte CCK_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte OFDM_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte OFDM_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte RSSI_Ant1_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte RSSI_Ant2_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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u1Byte TxAnt[ODM_ASSOCIATE_ENTRY_NUM];
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u1Byte TargetSTA;
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u1Byte antsel;
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u1Byte RxIdleAnt;
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#endif
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}SWAT_T, *pSWAT_T;
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#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
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#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
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typedef struct _BF_DIV_COEX_
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{
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BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM];
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BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
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u1Byte BDCcoexType_wBfer;
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u1Byte num_Txbfee_Client;
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u1Byte num_Txbfer_Client;
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u1Byte BDC_Try_counter;
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u1Byte BDC_Hold_counter;
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u1Byte BDC_Mode;
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u1Byte BDC_active_Mode;
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u1Byte BDC_state;
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u1Byte BDC_RxIdleUpdate_counter;
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u1Byte num_Client;
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u1Byte pre_num_Client;
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u1Byte num_BfTar;
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u1Byte num_DivTar;
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BOOLEAN bAll_DivSta_Idle;
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BOOLEAN bAll_BFSta_Idle;
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BOOLEAN BDC_Try_flag;
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BOOLEAN BF_pass;
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BOOLEAN DIV_pass;
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}BDC_T,*pBDC_T;
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#endif
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#endif
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typedef struct _FAST_ANTENNA_TRAINNING_
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{
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u1Byte Bssid[6];
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u1Byte antsel_rx_keep_0;
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u1Byte antsel_rx_keep_1;
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u1Byte antsel_rx_keep_2;
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u1Byte antsel_rx_keep_3;
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u4Byte antSumRSSI[7];
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u4Byte antRSSIcnt[7];
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u4Byte antAveRSSI[7];
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u1Byte FAT_State;
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u4Byte TrainIdx;
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u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
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u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
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u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u1Byte RxIdleAnt;
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u1Byte AntDiv_OnOff;
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BOOLEAN bBecomeLinked;
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u4Byte MinMaxRSSI;
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u1Byte idx_AntDiv_counter_2G;
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u1Byte idx_AntDiv_counter_5G;
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u1Byte AntDiv_2G_5G;
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u4Byte CCK_counter_main;
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u4Byte CCK_counter_aux;
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u4Byte OFDM_counter_main;
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u4Byte OFDM_counter_aux;
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#ifdef ODM_EVM_ENHANCE_ANTDIV
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u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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BOOLEAN EVM_method_enable;
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u1Byte TargetAnt_EVM;
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u1Byte TargetAnt_CRC32;
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u1Byte TargetAnt_enhance;
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u1Byte pre_TargetAnt_enhance;
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u2Byte Main_MPDU_OK_cnt;
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u2Byte Aux_MPDU_OK_cnt;
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u4Byte CRC32_Ok_Cnt;
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u4Byte CRC32_Fail_Cnt;
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u4Byte MainCRC32_Ok_Cnt;
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u4Byte AuxCRC32_Ok_Cnt;
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u4Byte MainCRC32_Fail_Cnt;
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u4Byte AuxCRC32_Fail_Cnt;
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#endif
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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u4Byte CCK_CtrlFrame_Cnt_main;
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u4Byte CCK_CtrlFrame_Cnt_aux;
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u4Byte OFDM_CtrlFrame_Cnt_main;
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u4Byte OFDM_CtrlFrame_Cnt_aux;
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u4Byte MainAnt_CtrlFrame_Sum;
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u4Byte AuxAnt_CtrlFrame_Sum;
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u4Byte MainAnt_CtrlFrame_Cnt;
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u4Byte AuxAnt_CtrlFrame_Cnt;
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#endif
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BOOLEAN fix_ant_bfee;
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BOOLEAN enable_ctrl_frame_antdiv;
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BOOLEAN use_ctrl_frame_antdiv;
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}FAT_T,*pFAT_T;
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//1 ============================================================
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//1 enumeration
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//1 ============================================================
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typedef enum _FAT_STATE
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{
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FAT_NORMAL_STATE = 0,
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FAT_TRAINING_STATE = 1,
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}FAT_STATE_E, *PFAT_STATE_E;
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typedef enum _ANT_DIV_TYPE
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{
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NO_ANTDIV = 0xFF,
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CG_TRX_HW_ANTDIV = 0x01,
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CGCS_RX_HW_ANTDIV = 0x02,
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FIXED_HW_ANTDIV = 0x03,
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CG_TRX_SMART_ANTDIV = 0x04,
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CGCS_RX_SW_ANTDIV = 0x05,
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S0S1_SW_ANTDIV = 0x06 //8723B intrnal switch S0 S1
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}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
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//1 ============================================================
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//1 function prototype
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//1 ============================================================
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VOID
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ODM_StopAntennaSwitchDm(
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IN PVOID pDM_VOID
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);
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VOID
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ODM_SetAntConfig(
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IN PVOID pDM_VOID,
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IN u1Byte antSetting // 0=A, 1=B, 2=C, ....
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);
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#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
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VOID ODM_SwAntDivRestAfterLink(
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IN PVOID pDM_VOID
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);
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#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
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VOID
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ODM_UpdateRxIdleAnt(
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IN PVOID pDM_VOID,
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IN u1Byte Ant
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);
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#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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VOID
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ODM_SW_AntDiv_Callback(
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IN PRT_TIMER pTimer
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);
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VOID
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ODM_SW_AntDiv_WorkitemCallback(
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IN PVOID pContext
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);
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#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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VOID
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ODM_SW_AntDiv_WorkitemCallback(
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IN PVOID pContext
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);
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VOID
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ODM_SW_AntDiv_Callback(
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void *FunctionContext
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);
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#endif
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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VOID
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odm_S0S1_SwAntDivByCtrlFrame(
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IN PVOID pDM_VOID,
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IN u1Byte Step
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);
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VOID
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odm_AntselStatisticsOfCtrlFrame(
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IN PVOID pDM_VOID,
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IN u1Byte antsel_tr_mux,
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IN u4Byte RxPWDBAll
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);
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VOID
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odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(
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IN PVOID pDM_VOID,
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IN PVOID p_phy_info_void,
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IN PVOID p_pkt_info_void
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);
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/*
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VOID
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odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(
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IN PVOID pDM_VOID,
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IN PVOID p_phy_info_void,
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IN PVOID p_pkt_info_void
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);
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*/
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#endif
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#endif
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#ifdef ODM_EVM_ENHANCE_ANTDIV
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VOID
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odm_EVM_FastAntTrainingCallback(
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IN PVOID pDM_VOID
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);
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#endif
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VOID
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odm_HW_AntDiv(
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IN PVOID pDM_VOID
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);
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#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
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VOID
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odm_FastAntTraining(
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IN PVOID pDM_VOID
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);
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VOID
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odm_FastAntTrainingCallback(
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IN PVOID pDM_VOID
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);
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VOID
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odm_FastAntTrainingWorkItemCallback(
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IN PVOID pDM_VOID
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);
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#endif
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VOID
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ODM_AntDivInit(
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IN PVOID pDM_VOID
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);
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VOID
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ODM_AntDiv(
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IN PVOID pDM_VOID
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);
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VOID
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odm_AntselStatistics(
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IN PVOID pDM_VOID,
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IN u1Byte antsel_tr_mux,
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IN u4Byte MacId,
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IN u4Byte utility,
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IN u1Byte method
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);
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/*
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VOID
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ODM_Process_RSSIForAntDiv(
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IN OUT PVOID pDM_VOID,
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IN PVOID p_phy_info_void,
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IN PVOID p_pkt_info_void
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);
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*/
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VOID
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ODM_Process_RSSIForAntDiv(
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IN OUT PVOID pDM_VOID,
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IN PVOID p_phy_info_void,
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IN PVOID p_pkt_info_void
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);
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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VOID
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ODM_SetTxAntByTxInfo(
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IN PVOID pDM_VOID,
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IN pu1Byte pDesc,
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IN u1Byte macId
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);
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#elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
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VOID
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ODM_SetTxAntByTxInfo(
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struct rtl8192cd_priv *priv,
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struct tx_desc *pdesc,
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unsigned short aid
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);
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#endif
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VOID
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ODM_AntDiv_Config(
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IN PVOID pDM_VOID
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);
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VOID
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ODM_UpdateRxIdleAnt_8723B(
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IN PVOID pDM_VOID,
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IN u1Byte Ant,
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IN u4Byte DefaultAnt,
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IN u4Byte OptionalAnt
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);
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VOID
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ODM_AntDivTimers(
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IN PVOID pDM_VOID,
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IN u1Byte state
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);
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#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
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VOID
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ODM_AntDivReset(
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IN PVOID pDM_VOID
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);
|
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VOID
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odm_AntennaDiversityInit(
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IN PVOID pDM_VOID
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);
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VOID
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odm_AntennaDiversity(
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IN PVOID pDM_VOID
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);
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#endif //#ifndef __ODMANTDIV_H__
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