/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2009-2012 Realtek Corporation.*/
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#ifndef __RTL8723E_PWRSEQCMD_H__
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#define __RTL8723E_PWRSEQCMD_H__
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#include "wifi.h"
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/*---------------------------------------------
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* 3 The value of cmd: 4 bits
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*---------------------------------------------
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*/
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#define PWR_CMD_READ 0x00
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#define PWR_CMD_WRITE 0x01
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#define PWR_CMD_POLLING 0x02
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#define PWR_CMD_DELAY 0x03
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#define PWR_CMD_END 0x04
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/* define the base address of each block */
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#define PWR_BASEADDR_MAC 0x00
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#define PWR_BASEADDR_USB 0x01
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#define PWR_BASEADDR_PCIE 0x02
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#define PWR_BASEADDR_SDIO 0x03
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#define PWR_INTF_SDIO_MSK BIT(0)
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#define PWR_INTF_USB_MSK BIT(1)
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#define PWR_INTF_PCI_MSK BIT(2)
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#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
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#define PWR_FAB_TSMC_MSK BIT(0)
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#define PWR_FAB_UMC_MSK BIT(1)
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#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
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#define PWR_CUT_TESTCHIP_MSK BIT(0)
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#define PWR_CUT_A_MSK BIT(1)
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#define PWR_CUT_B_MSK BIT(2)
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#define PWR_CUT_C_MSK BIT(3)
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#define PWR_CUT_D_MSK BIT(4)
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#define PWR_CUT_E_MSK BIT(5)
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#define PWR_CUT_F_MSK BIT(6)
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#define PWR_CUT_G_MSK BIT(7)
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#define PWR_CUT_ALL_MSK 0xFF
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enum pwrseq_delay_unit {
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PWRSEQ_DELAY_US,
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PWRSEQ_DELAY_MS,
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};
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struct wlan_pwr_cfg {
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u16 offset;
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u8 cut_msk;
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u8 fab_msk:4;
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u8 interface_msk:4;
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u8 base:4;
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u8 cmd:4;
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u8 msk;
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u8 value;
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};
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#define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset)
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#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk)
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#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk)
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#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk)
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#define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base)
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#define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd)
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#define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk)
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#define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value)
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bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
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u8 fab_version, u8 interface_type,
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struct wlan_pwr_cfg pwrcfgcmd[]);
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#endif
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